Commit a812b09a authored by Alex Elder's avatar Alex Elder Committed by Manivannan Sadhasivam
Browse files

dt-bindings: pci: spacemit: Introduce PCIe host controller 



Add the Devicetree binding for the PCIe Root Complex found on the SpacemiT
K1 SoC.  This Root Complex is derived from the Synopsys Designware PCIe IP.
It supports up to three PCIe ports operating at PCIe link speed up to 5
GT/sec. One of the ports uses a combo PHY, which is typically used to
support a USB3 port.

Signed-off-by: default avatarAlex Elder <elder@riscstar.com>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Tested-by: default avatarJason Montleon <jmontleo@redhat.com>
Tested-by: default avatarJohannes Erdfelt <johannes@erdfelt.com>
Tested-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251113214540.2623070-4-elder@riscstar.com
parent 3a866087

Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: SpacemiT K1 PCI Express Host Controller



maintainers:

  - Alex Elder <elder@riscstar.com>



description: >

  The SpacemiT K1 SoC PCIe host controller is based on the Synopsys DesignWare

  PCIe IP.  The controller uses the DesignWare built-in MSI interrupt

  controller, and supports 256 MSIs.



allOf:

  - $ref: /schemas/pci/snps,dw-pcie.yaml#



properties:

  compatible:

    const: spacemit,k1-pcie



  reg:

    items:

      - description: DesignWare PCIe registers

      - description: ATU address space

      - description: PCIe configuration space

      - description: Link control registers



  reg-names:

    items:

      - const: dbi

      - const: atu

      - const: config

      - const: link



  clocks:

    items:

      - description: DWC PCIe Data Bus Interface (DBI) clock

      - description: DWC PCIe application AXI-bus master interface clock

      - description: DWC PCIe application AXI-bus slave interface clock



  clock-names:

    items:

      - const: dbi

      - const: mstr

      - const: slv



  resets:

    items:

      - description: DWC PCIe Data Bus Interface (DBI) reset

      - description: DWC PCIe application AXI-bus master interface reset

      - description: DWC PCIe application AXI-bus slave interface reset



  reset-names:

    items:

      - const: dbi

      - const: mstr

      - const: slv



  interrupts:

    items:

      - description: Interrupt used for MSIs



  interrupt-names:

    const: msi



  spacemit,apmu:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description:

      A phandle that refers to the APMU system controller, whose regmap is

      used in managing resets and link state, along with and offset of its

      reset control register.

    items:

      - items:

          - description: phandle to APMU system controller

          - description: register offset



patternProperties:

  '^pcie@':

    type: object

    $ref: /schemas/pci/pci-pci-bridge.yaml#



    properties:

      phys:

        maxItems: 1



      vpcie3v3-supply:

        description:

          A phandle for 3.3v regulator to use for PCIe



    required:

      - phys

      - vpcie3v3-supply



    unevaluatedProperties: false



required:

  - clocks

  - clock-names

  - resets

  - reset-names

  - interrupts

  - interrupt-names

  - spacemit,apmu



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/spacemit,k1-syscon.h>

    pcie@ca400000 {

        device_type = "pci";

        compatible = "spacemit,k1-pcie";

        reg = <0xca400000 0x00001000>,

              <0xca700000 0x0001ff24>,

              <0x9f000000 0x00002000>,

              <0xc0c20000 0x00001000>;

        reg-names = "dbi",

                    "atu",

                    "config",

                    "link";

        #address-cells = <3>;

        #size-cells = <2>;

        ranges = <0x01000000 0x0 0x00000000 0x9f002000 0x0 0x00100000>,

                 <0x02000000 0x0 0x90000000 0x90000000 0x0 0x0f000000>;

        interrupts = <142>;

        interrupt-names = "msi";

        clocks = <&syscon_apmu CLK_PCIE1_DBI>,

                 <&syscon_apmu CLK_PCIE1_MASTER>,

                 <&syscon_apmu CLK_PCIE1_SLAVE>;

        clock-names = "dbi",

                      "mstr",

                      "slv";

        resets = <&syscon_apmu RESET_PCIE1_DBI>,

                 <&syscon_apmu RESET_PCIE1_MASTER>,

                 <&syscon_apmu RESET_PCIE1_SLAVE>;

        reset-names = "dbi",

                      "mstr",

                      "slv";

        pinctrl-names = "default";

        pinctrl-0 = <&pcie1_3_cfg>;

        spacemit,apmu = <&syscon_apmu 0x3d4>;



        pcie@0 {

          device_type = "pci";

          compatible = "pciclass,0604";

          reg = <0x0 0x0 0x0 0x0 0x0>;

          bus-range = <0x01 0xff>;

          #address-cells = <3>;

          #size-cells = <2>;

          ranges;

          phys = <&pcie1_phy>;

          vpcie3v3-supply = <&pcie_vcc_3v3>;

        };

    };