Commit a84a9ba7 authored by Naomi Chu's avatar Naomi Chu Committed by Martin K. Petersen
Browse files

scsi: ufs: host: mediatek: Add DDR_EN setting



On MT6989 and later platforms, control of DDR_EN has been switched from
SPM to EMI. To prevent abnormal access to DRAM, it is necessary to wait
for 'ddren_ack' or assert 'ddren_urgent' after sending 'ddren_req'.

Introduce the DDR_EN configuration in the UFS initialization flow,
utilizing the assertion of 'ddren_urgent' to maintain performance.

Signed-off-by: default avatarNaomi Chu <naomi.chu@mediatek.com>
Link: https://lore.kernel.org/r/20250722030841.1998783-3-peter.wang@mediatek.com


Reviewed-by: default avatarPeter Wang <peter.wang@mediatek.com>
Reviewed-by: default avatarChun-Hung Wu <chun-hung.wu@mediatek.com>
Signed-off-by: default avatarPeter Wang <peter.wang@mediatek.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 26289393
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+7 −0
Original line number Diff line number Diff line
@@ -267,6 +267,13 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
		ufshcd_writel(hba,
			      ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80,
			      REG_UFS_XOUFS_CTRL);

		/* DDR_EN setting */
		if (host->ip_ver >= IP_VER_MT6989) {
			ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8),
				0x453000, REG_UFS_MMIO_OPT_CTRL_0);
		}

	}

	return 0;
+12 −0
Original line number Diff line number Diff line
@@ -192,4 +192,16 @@ struct ufs_mtk_host {
/* MTK RTT support number */
#define MTK_MAX_NUM_RTT 2

/* UFSHCI MTK ip version value */
enum {
	/* UFSHCI 3.1 */
	IP_VER_MT6878    = 0x10420200,

	/* UFSHCI 4.0 */
	IP_VER_MT6897    = 0x10440000,
	IP_VER_MT6989    = 0x10450000,

	IP_VER_NONE      = 0xFFFFFFFF
};

#endif /* !_UFS_MEDIATEK_H */