Commit a86a3aa5 authored by Martin K. Petersen's avatar Martin K. Petersen
Browse files

Merge patch series "mpi3mr: Few Enhancements and minor fixes"

Ranjan Kumar <ranjan.kumar@broadcom.com> says:

Few Enhancements and minor fixes of mpi3mr driver.

Link: https://lore.kernel.org/r/20240313100746.128951-1-ranjan.kumar@broadcom.com


Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parents e831b92b 829dce7e
Loading
Loading
Loading
Loading
+3 −0
Original line number Diff line number Diff line
@@ -309,6 +309,7 @@ struct mpi3_man6_gpio_entry {
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC                     (0x00)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT                  (0x10)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT    (0x20)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED                       (0x02)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK                       (0x01)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE                       (0x00)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL                      (0x01)
@@ -1315,6 +1316,8 @@ struct mpi3_driver_page0 {
	__le32                             reserved18;
};
#define MPI3_DRIVER0_PAGEVERSION               (0x00)
#define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE	    (0x00000020)
#define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE		    (0x00000010)
#define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE           (0x00000008)
#define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL            (0x00000004)
#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK              (0x00000003)
+5 −15
Original line number Diff line number Diff line
@@ -198,16 +198,17 @@ struct mpi3_supported_devices_data {
	struct mpi3_supported_device   supported_device[MPI3_SUPPORTED_DEVICE_MAX];
};

#ifndef MPI3_ENCRYPTED_HASH_MAX
#define MPI3_ENCRYPTED_HASH_MAX                      (1)
#ifndef MPI3_PUBLIC_KEY_MAX
#define MPI3_PUBLIC_KEY_MAX                      (1)
#endif
struct mpi3_encrypted_hash_entry {
	u8                         hash_image_type;
	u8                         hash_algorithm;
	u8                         encryption_algorithm;
	u8                         reserved03;
	__le32                     reserved04;
	__le32                     encrypted_hash[MPI3_ENCRYPTED_HASH_MAX];
	__le16                     public_key_size;
	__le16                     signature_size;
	__le32                     public_key[MPI3_PUBLIC_KEY_MAX];
};

#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE      (0x03)
@@ -228,17 +229,6 @@ struct mpi3_encrypted_hash_entry {
#define MPI3_ENCRYPTION_ALGORITHM_RSA2048            (0x04)
#define MPI3_ENCRYPTION_ALGORITHM_RSA4096            (0x05)
#define MPI3_ENCRYPTION_ALGORITHM_RSA3072            (0x06)
#ifndef MPI3_PUBLIC_KEY_MAX
#define MPI3_PUBLIC_KEY_MAX                          (1)
#endif
struct mpi3_encrypted_key_with_hash_entry {
	u8                         hash_image_type;
	u8                         hash_algorithm;
	u8                         encryption_algorithm;
	u8                         reserved03;
	__le32                     reserved04;
	__le32                     public_key[MPI3_PUBLIC_KEY_MAX];
};

#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX
#define MPI3_ENCRYPTED_HASH_ENTRY_MAX               (1)
+12 −8
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ struct mpi3_ioc_init_request {
	__le64                   sense_buffer_free_queue_address;
	__le64                   driver_information_address;
};

#define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED		(0x08)
#define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED	(0x04)
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK          (0x03)
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED      (0x00)
@@ -101,6 +101,8 @@ struct mpi3_ioc_facts_data {
	__le16                     max_io_throttle_group;
	__le16                     io_throttle_low;
	__le16                     io_throttle_high;
	__le32			   diag_fdl_size;
	__le32			   diag_tty_size;
};
#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK          (0x80000000)
#define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC               (0x00000000)
@@ -108,13 +110,13 @@ struct mpi3_ioc_facts_data {
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK            (0x00000600)
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000)
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO  (0x00000200)
#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE       (0x00000100)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED       (0x00000080)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED          (0x00000040)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED      (0x00000020)
#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED     (0x00000010)
#define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE                 (0x00000008)
#define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED            (0x00000002)
#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED     (0x00000100)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED     (0x00000080)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_SUPPORTED        (0x00000040)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_SUPPORTED    (0x00000020)
#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_SUPPORTED   (0x00000010)
#define MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED               (0x00000008)
#define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED          (0x00000002)
#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED      (0x00000001)
#define MPI3_IOCFACTS_PID_TYPE_MASK                           (0xf000)
#define MPI3_IOCFACTS_PID_TYPE_SHIFT                          (12)
@@ -159,6 +161,8 @@ struct mpi3_ioc_facts_data {
#define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR              (0x00000002)
#define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED    (0x0000)
#define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED      (0x0000)
#define MPI3_IOCFACTS_DIAGFDLSIZE_NOT_SUPPORTED		      (0x00000000)
#define MPI3_IOCFACTS_DIAGTTYSIZE_NOT_SUPPORTED               (0x00000000)
struct mpi3_mgmt_passthrough_request {
	__le16                 host_tag;
	u8                     ioc_use_only02;
+1 −1
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ union mpi3_version_union {

#define MPI3_VERSION_MAJOR                                              (3)
#define MPI3_VERSION_MINOR                                              (0)
#define MPI3_VERSION_UNIT                                               (28)
#define MPI3_VERSION_UNIT                                               (31)
#define MPI3_VERSION_DEV                                                (0)
#define MPI3_DEVHANDLE_INVALID                                          (0xffff)
struct mpi3_sysif_oper_queue_indexes {
+10 −6
Original line number Diff line number Diff line
@@ -55,15 +55,15 @@ extern struct list_head mrioc_list;
extern int prot_mask;
extern atomic64_t event_counter;

#define MPI3MR_DRIVER_VERSION	"8.5.1.0.0"
#define MPI3MR_DRIVER_RELDATE	"5-December-2023"
#define MPI3MR_DRIVER_VERSION	"8.8.1.0.50"
#define MPI3MR_DRIVER_RELDATE	"5-March-2024"

#define MPI3MR_DRIVER_NAME	"mpi3mr"
#define MPI3MR_DRIVER_LICENSE	"GPL"
#define MPI3MR_DRIVER_AUTHOR	"Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
#define MPI3MR_DRIVER_DESC	"MPI3 Storage Controller Device Driver"

#define MPI3MR_NAME_LENGTH	32
#define MPI3MR_NAME_LENGTH	64
#define IOCNAME			"%s: "

#define MPI3MR_DEFAULT_MAX_IO_SIZE	(1 * 1024 * 1024)
@@ -294,6 +294,10 @@ enum mpi3mr_reset_reason {
	MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30,
};

#define MPI3MR_RESET_REASON_OSTYPE_LINUX	1
#define MPI3MR_RESET_REASON_OSTYPE_SHIFT	28
#define MPI3MR_RESET_REASON_IOCNUM_SHIFT	20

/* Queue type definitions */
enum queue_type {
	MPI3MR_DEFAULT_QUEUE = 0,
@@ -1142,7 +1146,7 @@ struct mpi3mr_ioc {
	spinlock_t fwevt_lock;
	struct list_head fwevt_list;

	char watchdog_work_q_name[20];
	char watchdog_work_q_name[50];
	struct workqueue_struct *watchdog_work_q;
	struct delayed_work watchdog_work;
	spinlock_t watchdog_lock;
@@ -1336,7 +1340,7 @@ void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);

int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
			      u32 reset_reason, u8 snapdump);
			      u16 reset_reason, u8 snapdump);
void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);

@@ -1348,7 +1352,7 @@ void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
void mpi3mr_refresh_tgtdevs(struct mpi3mr_ioc *mrioc);
void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
Loading