Commit a8943f7f authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: rzv2h: Use GENMASK for PLL fields 



Replace the older FIELD_GET-wrapping helper macros with plain GENMASK
definitions for the PLL CLK1/CLK2 field masks (CPG_PLL_CLK1_KDIV,
CPG_PLL_CLK1_MDIV, CPG_PLL_CLK1_PDIV and CPG_PLL_CLK2_SDIV). Update
rzv2h_cpg_pll_clk_recalc_rate() to explicitly extract those fields with
FIELD_GET and cast the KDIV extraction to s16 to ensure proper sign
extension when computing the PLL output rate.

Co-developed-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarTomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251015192611.241920-3-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 36a23904

drivers/clk/renesas/rzv2h-cpg.c

+8 −7
Original line number Diff line number Diff line
@@ -49,11 +49,11 @@ 
#define CPG_PLL_STBY_RESETB	BIT(0)

#define CPG_PLL_STBY_RESETB_WEN	BIT(16)

#define CPG_PLL_CLK1(x)		((x) + 0x004)

#define CPG_PLL_CLK1_KDIV(x)	((s16)FIELD_GET(GENMASK(31, 16), (x)))

#define CPG_PLL_CLK1_MDIV(x)	FIELD_GET(GENMASK(15, 6), (x))

#define CPG_PLL_CLK1_PDIV(x)	FIELD_GET(GENMASK(5, 0), (x))

#define CPG_PLL_CLK1_KDIV	GENMASK(31, 16)

#define CPG_PLL_CLK1_MDIV	GENMASK(15, 6)

#define CPG_PLL_CLK1_PDIV	GENMASK(5, 0)

#define CPG_PLL_CLK2(x)		((x) + 0x008)

#define CPG_PLL_CLK2_SDIV(x)	FIELD_GET(GENMASK(2, 0), (x))

#define CPG_PLL_CLK2_SDIV	GENMASK(2, 0)

#define CPG_PLL_MON(x)		((x) + 0x010)

#define CPG_PLL_MON_RESETB	BIT(0)

#define CPG_PLL_MON_LOCK	BIT(4)
@@ -231,10 +231,11 @@ static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw, 
	clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset));

	clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset));



	rate = mul_u64_u32_shr(parent_rate, (CPG_PLL_CLK1_MDIV(clk1) << 16) +

			       CPG_PLL_CLK1_KDIV(clk1), 16 + CPG_PLL_CLK2_SDIV(clk2));

	rate = mul_u64_u32_shr(parent_rate, (FIELD_GET(CPG_PLL_CLK1_MDIV, clk1) << 16) +

			       (s16)FIELD_GET(CPG_PLL_CLK1_KDIV, clk1),

			       16 + FIELD_GET(CPG_PLL_CLK2_SDIV, clk2));



	return DIV_ROUND_CLOSEST_ULL(rate, CPG_PLL_CLK1_PDIV(clk1));

	return DIV_ROUND_CLOSEST_ULL(rate, FIELD_GET(CPG_PLL_CLK1_PDIV, clk1));

}



static const struct clk_ops rzv2h_cpg_pll_ops = {