Commit a8ac994c authored by Cruise's avatar Cruise Committed by Alex Deucher
Browse files

drm/amd/display: Disable error correction if it's not supported 



[Why]
Error correction was enabled in a monitor which doesn't support.

[How]
Disable error correction if it's not supported

Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarCruise <cruise.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2862b163

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

+21 −26
Original line number Diff line number Diff line
@@ -147,32 +147,27 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource 


	link_enc = link_enc_cfg_get_link_enc(link);

	ASSERT(link_enc);

	if (link_enc->funcs->fec_set_ready == NULL)

		return DC_NOT_SUPPORTED;



	if (!dp_should_enable_fec(link))

		return status;



	if (link_enc->funcs->fec_set_ready &&

			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {

		if (ready) {

	if (ready && dp_should_enable_fec(link)) {

		if (link->fec_state == dc_link_fec_not_ready) {

			fec_config = 1;

			status = core_link_write_dpcd(link,

					DP_FEC_CONFIGURATION,

					&fec_config,

					sizeof(fec_config));



			status = core_link_write_dpcd(link, DP_FEC_CONFIGURATION,

					&fec_config, sizeof(fec_config));



			if (status == DC_OK) {

				link_enc->funcs->fec_set_ready(link_enc, true);

				link->fec_state = dc_link_fec_ready;

			} else {

				link_enc->funcs->fec_set_ready(link_enc, false);

				link->fec_state = dc_link_fec_not_ready;

				dm_error("dpcd write failed to set fec_ready");

			}

		} else if (link->fec_state == dc_link_fec_ready) {

		}

	} else {

		if (link->fec_state == dc_link_fec_ready) {

			fec_config = 0;

			status = core_link_write_dpcd(link,

					DP_FEC_CONFIGURATION,

					&fec_config,

					sizeof(fec_config));

			core_link_write_dpcd(link, DP_FEC_CONFIGURATION,

				&fec_config, sizeof(fec_config));



			link_enc->funcs->fec_set_ready(link_enc, false);

			link->fec_state = dc_link_fec_not_ready;

		}
@@ -187,14 +182,12 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) 


	link_enc = link_enc_cfg_get_link_enc(link);

	ASSERT(link_enc);



	if (!dp_should_enable_fec(link))

	if (link_enc->funcs->fec_set_enable == NULL)

		return;



	if (link_enc->funcs->fec_set_enable &&

			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {

		if (link->fec_state == dc_link_fec_ready && enable) {

			/* Accord to DP spec, FEC enable sequence can first

	if (enable && dp_should_enable_fec(link)) {

		if (link->fec_state == dc_link_fec_ready) {

			/* According to DP spec, FEC enable sequence can first

			 * be transmitted anytime after 1000 LL codes have

			 * been transmitted on the link after link training

			 * completion. Using 1 lane RBR should have the maximum
@@ -204,7 +197,9 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) 
			udelay(7);

			link_enc->funcs->fec_set_enable(link_enc, true);

			link->fec_state = dc_link_fec_enabled;

		} else if (link->fec_state == dc_link_fec_enabled && !enable) {

		}

	} else {

		if (link->fec_state == dc_link_fec_enabled) {

			link_enc->funcs->fec_set_enable(link_enc, false);

			link->fec_state = dc_link_fec_ready;

		}