Commit a8cb4514 authored by Sohil Mehta's avatar Sohil Mehta Committed by Ingo Molnar
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x86/mtrr: Modify a x86_model check to an Intel VFM check 



Simplify one of the last few Intel x86_model checks in arch/x86 by
substituting it with a VFM one.

Signed-off-by: default avatarSohil Mehta <sohil.mehta@intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Acked-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/r/20250219184133.816753-5-sohil.mehta@intel.com
parent 7e6b0a2e

arch/x86/kernel/cpu/mtrr/generic.c

+2 −2
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <asm/processor-flags.h>

#include <asm/cacheinfo.h>

#include <asm/cpufeature.h>

#include <asm/cpu_device_id.h>

#include <asm/hypervisor.h>

#include <asm/mshyperv.h>

#include <asm/tlbflush.h>
@@ -1026,8 +1027,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size, 
	 * For Intel PPro stepping <= 7

	 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF

	 */

	if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86 == 6 &&

	    boot_cpu_data.x86_model == 1 &&

	if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO &&

	    boot_cpu_data.x86_stepping <= 7) {

		if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {

			pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);