Commit a8ed59a3 authored by Tony Luck's avatar Tony Luck Committed by Ingo Molnar
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Documentation/x86: Document that resctrl bandwidth control units are MiB 



The memory bandwidth software controller uses 2^20 units rather than
10^6. See mbm_bw_count() which computes bandwidth using the "SZ_1M"
Linux define for 0x00100000.

Update the documentation to use MiB when describing this feature.
It's too late to fix the mount option "mba_MBps" as that is now an
established user interface.

Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20240322182016.196544-1-tony.luck@intel.com
parent f2208aa1

Documentation/arch/x86/resctrl.rst

+4 −4
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ mount options are: 
	Enable code/data prioritization in L2 cache allocations.

"mba_MBps":

	Enable the MBA Software Controller(mba_sc) to specify MBA

	bandwidth in MBps

	bandwidth in MiBps

"debug":

	Make debug files accessible. Available debug files are annotated with

	"Available only with debug option".
@@ -526,7 +526,7 @@ threads start using more cores in an rdtgroup, the actual bandwidth may 
increase or vary although user specified bandwidth percentage is same.



In order to mitigate this and make the interface more user friendly,

resctrl added support for specifying the bandwidth in MBps as well.  The

resctrl added support for specifying the bandwidth in MiBps as well.  The

kernel underneath would use a software feedback mechanism or a "Software

Controller(mba_sc)" which reads the actual bandwidth using MBM counters

and adjust the memory bandwidth percentages to ensure::
@@ -573,13 +573,13 @@ Memory b/w domain is L3 cache. 


	MB:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...



Memory bandwidth Allocation specified in MBps

Memory bandwidth Allocation specified in MiBps

---------------------------------------------



Memory bandwidth domain is L3 cache.

::



	MB:<cache_id0>=bw_MBps0;<cache_id1>=bw_MBps1;...

	MB:<cache_id0>=bw_MiBps0;<cache_id1>=bw_MiBps1;...



Slow Memory Bandwidth Allocation (SMBA)

---------------------------------------