Commit a8fed1bc authored by Aleksa Paunovic's avatar Aleksa Paunovic Committed by Paul Walmsley
Browse files

riscv: Add xmipsexectl as a vendor extension 



Add support for MIPS vendor extensions. Add support for the xmipsexectl
vendor extension.

Signed-off-by: default avatarAleksa Paunovic <aleksa.paunovic@htecgroup.com>
Reviewed-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-2-a6cbbe1c3412@htecgroup.com


[pjw@kernel.org: added the MIPS vendor ID from another patch to fix the build]
Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent f79671dc

arch/riscv/Kconfig.vendor

+13 −0
Original line number Diff line number Diff line
@@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES 
	  If you don't know what to do here, say Y.

endmenu



menu "MIPS"

config RISCV_ISA_VENDOR_EXT_MIPS

	bool "MIPS vendor extension support"

	select RISCV_ISA_VENDOR_EXT

	default y

	help

	  Say N here to disable detection of and support for all MIPS vendor

	  extensions. Without this option enabled, MIPS vendor extensions will

	  not be detected at boot and their presence not reported to userspace.



	  If you don't know what to do here, say Y.

endmenu



menu "SiFive"

config RISCV_ISA_VENDOR_EXT_SIFIVE

	bool "SiFive vendor extension support"

arch/riscv/include/asm/vendor_extensions/mips.h

0 → 100644
+18 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2025 MIPS.

 */



#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H

#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H



#include <linux/types.h>



#define RISCV_ISA_VENDOR_EXT_XMIPSEXECTL	0



#ifndef __ASSEMBLER__

struct riscv_isa_vendor_ext_data_list;

extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;

#endif



#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H

arch/riscv/include/asm/vendorid_list.h

+1 −0
Original line number Diff line number Diff line
@@ -9,5 +9,6 @@ 
#define MICROCHIP_VENDOR_ID	0x029

#define SIFIVE_VENDOR_ID	0x489

#define THEAD_VENDOR_ID		0x5b7

#define MIPS_VENDOR_ID		0x722



#endif

arch/riscv/kernel/vendor_extensions.c

+10 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <asm/vendorid_list.h>

#include <asm/vendor_extensions.h>

#include <asm/vendor_extensions/andes.h>

#include <asm/vendor_extensions/mips.h>

#include <asm/vendor_extensions/sifive.h>

#include <asm/vendor_extensions/thead.h>
@@ -16,6 +17,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = { 
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES

	&riscv_isa_vendor_ext_list_andes,

#endif

#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS

	&riscv_isa_vendor_ext_list_mips,

#endif

#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE

	&riscv_isa_vendor_ext_list_sifive,

#endif
@@ -49,6 +53,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig 
		cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;

		break;

	#endif

	#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS

	case MIPS_VENDOR_ID:

		bmap = &riscv_isa_vendor_ext_list_mips.all_harts_isa_bitmap;

		cpu_bmap = riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap;

		break;

	#endif

	#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE

	case SIFIVE_VENDOR_ID:

		bmap = &riscv_isa_vendor_ext_list_sifive.all_harts_isa_bitmap;

arch/riscv/kernel/vendor_extensions/Makefile

+1 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only



obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)	+= andes.o

obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)  	+= mips.o

obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive.o

obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive_hwprobe.o

obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead.o