Commit a9108b07 authored Jul 30, 2023 by Christian Marangi Committed by Paolo Abeni Aug 01, 2023

net: dsa: qca8k: move qca8xxx hol fixup to separate function



Move qca8xxx hol fixup to separate function to tidy things up and to
permit using a more efficent loop in future patch.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20230730074113.21889-4-ansuelsmth@gmail.com


Signed-off-by: Paolo Abeni <pabeni@redhat.com>

parent 18e8feae

drivers/net/dsa/qca/qca8k-8xxx.c

+42 −36

Original line number	Diff line number	Diff line
		@@ -1756,6 +1756,46 @@ static int qca8k_connect_tag_protocol(struct dsa_switch *ds,
		return 0;
		}

		static void qca8k_setup_hol_fixup(struct qca8k_priv *priv, int port)
		{
		u32 mask;

		switch (port) {
		/* The 2 CPU port and port 5 requires some different
		* priority than any other ports.
		*/
		case 0:
		case 5:
		case 6:
		mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) \|
		QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
		break;
		default:
		mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) \|
		QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
		}
		regmap_write(priv->regmap, QCA8K_REG_PORT_HOL_CTRL0(port), mask);

		mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) \|
		QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN \|
		QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN \|
		QCA8K_PORT_HOL_CTRL1_WRED_EN;
		regmap_update_bits(priv->regmap, QCA8K_REG_PORT_HOL_CTRL1(port),
		QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK \|
		QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN \|
		QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN \|
		QCA8K_PORT_HOL_CTRL1_WRED_EN,
		mask);
		}

		static int
		qca8k_setup(struct dsa_switch *ds)
		{
		@@ -1895,42 +1935,8 @@ qca8k_setup(struct dsa_switch *ds)
		* missing settings to improve switch stability under load condition.
		* This problem is limited to qca8337 and other qca8k switch are not affected.
		*/
		if (priv->switch_id == QCA8K_ID_QCA8337) {
		switch (i) {
		/* The 2 CPU port and port 5 requires some different
		* priority than any other ports.
		*/
		case 0:
		case 5:
		case 6:
		mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) \|
		QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
		break;
		default:
		mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) \|
		QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) \|
		QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
		}
		qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);

		mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) \|
		QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN \|
		QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN \|
		QCA8K_PORT_HOL_CTRL1_WRED_EN;
		qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
		QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK \|
		QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN \|
		QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN \|
		QCA8K_PORT_HOL_CTRL1_WRED_EN,
		mask);
		}
		if (priv->switch_id == QCA8K_ID_QCA8337)
		qca8k_setup_hol_fixup(priv, i);
		}

		/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */