Commit a9425323 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
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arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node 



Add versa3 clock generator node. It provides the clocks for the Ethernet
PHY, PCIe, audio devices.

Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241210170953.2936724-22-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 880f6c84

arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -87,6 +87,12 @@ vcc_sdhi2: regulator2 { 
		gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	x3_clk: x3-clock {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <24000000>;

	};

};



&adc {
@@ -151,6 +157,30 @@ &extal_clk { 


&i2c1 {

	status = "okay";



	versa3: clock-generator@68 {

		compatible = "renesas,5l35023";

		reg = <0x68>;

		clocks = <&x3_clk>;

		#clock-cells = <1>;

		assigned-clocks = <&versa3 0>,

				  <&versa3 1>,

				  <&versa3 2>,

				  <&versa3 3>,

				  <&versa3 4>,

				  <&versa3 5>;

		assigned-clock-rates = <24000000>,

				       <12288000>,

				       <11289600>,

				       <25000000>,

				       <100000000>,

				       <100000000>;

		renesas,settings = [

		  80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27

		  00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86

		  a0 80 30 30 9c

		];

	};

};



#if SW_CONFIG2 == SW_ON