Commit a9445211 authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/idreg: Add overrride for GCS 



Hook up an override for GCS, allowing it to be disabled from the command
line by specifying arm64.nogcs in case there are problems.

Reviewed-by: default avatarThiago Jung Bauermann <thiago.bauermann@linaro.org>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20241001-arm64-gcs-v13-17-222b78d87eee@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 6497b66b

Documentation/admin-guide/kernel-parameters.txt

+3 −0
Original line number Diff line number Diff line
@@ -446,6 +446,9 @@ 
	arm64.nobti	[ARM64] Unconditionally disable Branch Target

			Identification support



	arm64.nogcs	[ARM64] Unconditionally disable Guarded Control Stack

			support



	arm64.nomops	[ARM64] Unconditionally disable Memory Copy and Memory

			Set instructions support

arch/arm64/kernel/pi/idreg-override.c

+2 −0
Original line number Diff line number Diff line
@@ -133,6 +133,7 @@ static const struct ftr_set_desc pfr1 __prel64_initconst = { 
	.override	= &id_aa64pfr1_override,

	.fields		= {

		FIELD("bt", ID_AA64PFR1_EL1_BT_SHIFT, NULL ),

		FIELD("gcs", ID_AA64PFR1_EL1_GCS_SHIFT, NULL),

		FIELD("mte", ID_AA64PFR1_EL1_MTE_SHIFT, NULL),

		FIELD("sme", ID_AA64PFR1_EL1_SME_SHIFT, pfr1_sme_filter),

		{}
@@ -215,6 +216,7 @@ static const struct { 
	{ "arm64.nosve",		"id_aa64pfr0.sve=0" },

	{ "arm64.nosme",		"id_aa64pfr1.sme=0" },

	{ "arm64.nobti",		"id_aa64pfr1.bt=0" },

	{ "arm64.nogcs",		"id_aa64pfr1.gcs=0" },

	{ "arm64.nopauth",

	  "id_aa64isar1.gpi=0 id_aa64isar1.gpa=0 "

	  "id_aa64isar1.api=0 id_aa64isar1.apa=0 "