Commit a9552153 authored by Suman Kumar Chakraborty's avatar Suman Kumar Chakraborty Committed by Herbert Xu
Browse files

crypto: qat - add adf_rl_get_num_svc_aes() in rate limiting 



Enhance the rate limiting (RL) infrastructure by adding
adf_rl_get_num_svc_aes() which can be used to fetch the number of engines
associated with the service type. Expand the structure adf_rl_hw_data
with an array that contains the number of AEs per service.

Implement adf_gen4_init_num_svc_aes() for QAT GEN4 devices to calculate
the total number of acceleration engines dedicated to a specific service.

Signed-off-by: default avatarSuman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent fdf31c75

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

+2 −0
Original line number Diff line number Diff line
@@ -301,6 +301,8 @@ static void adf_init_rl_data(struct adf_rl_hw_data *rl_data) 
	rl_data->max_tp[SVC_DC] = ADF_420XX_RL_MAX_TP_DC;

	rl_data->scan_interval = ADF_420XX_RL_SCANS_PER_SEC;

	rl_data->scale_ref = ADF_420XX_RL_SLICE_REF;



	adf_gen4_init_num_svc_aes(rl_data);

}



static int get_rp_group(struct adf_accel_dev *accel_dev, u32 ae_mask)

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

+2 −0
Original line number Diff line number Diff line
@@ -227,6 +227,8 @@ static void adf_init_rl_data(struct adf_rl_hw_data *rl_data) 
	rl_data->max_tp[SVC_DC] = ADF_4XXX_RL_MAX_TP_DC;

	rl_data->scan_interval = ADF_4XXX_RL_SCANS_PER_SEC;

	rl_data->scale_ref = ADF_4XXX_RL_SLICE_REF;



	adf_gen4_init_num_svc_aes(rl_data);

}



static u32 uof_get_num_objs(struct adf_accel_dev *accel_dev)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

+22 −0
Original line number Diff line number Diff line
@@ -558,3 +558,25 @@ void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops) 
	dc_ops->build_decomp_block = adf_gen4_build_decomp_block;

}

EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops);



void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data)

{

	struct adf_hw_device_data *hw_data;

	unsigned int i;

	u32 ae_cnt;



	hw_data = container_of(device_data, struct adf_hw_device_data, rl_data);

	ae_cnt = hweight32(hw_data->get_ae_mask(hw_data));

	if (!ae_cnt)

		return;



	for (i = 0; i < SVC_BASE_COUNT; i++)

		device_data->svc_ae_mask[i] = ae_cnt - 1;



	/*

	 * The decompression service is not supported on QAT GEN4 devices.

	 * Therefore, set svc_ae_mask to 0.

	 */

	device_data->svc_ae_mask[SVC_DECOMP] = 0;

}

EXPORT_SYMBOL_GPL(adf_gen4_init_num_svc_aes);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h

+1 −0
Original line number Diff line number Diff line
@@ -175,5 +175,6 @@ void adf_gen4_bank_drain_finish(struct adf_accel_dev *accel_dev, 
				u32 bank_number);

bool adf_gen4_services_supported(unsigned long service_mask);

void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops);

void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data);



#endif

drivers/crypto/intel/qat/qat_common/adf_rl.c

+12 −1
Original line number Diff line number Diff line
@@ -552,6 +552,17 @@ u32 adf_rl_calculate_slice_tokens(struct adf_accel_dev *accel_dev, u32 sla_val, 
	return allocated_tokens;

}



static u32 adf_rl_get_num_svc_aes(struct adf_accel_dev *accel_dev,

				  enum adf_base_services svc)

{

	struct adf_rl_hw_data *device_data = &accel_dev->hw_device->rl_data;



	if (svc >= SVC_BASE_COUNT)

		return 0;



	return device_data->svc_ae_mask[svc];

}



u32 adf_rl_calculate_ae_cycles(struct adf_accel_dev *accel_dev, u32 sla_val,

			       enum adf_base_services svc_type)

{
@@ -563,7 +574,7 @@ u32 adf_rl_calculate_ae_cycles(struct adf_accel_dev *accel_dev, u32 sla_val, 
		return 0;



	avail_ae_cycles = hw_data->clock_frequency;

	avail_ae_cycles *= hw_data->get_num_aes(hw_data) - 1;

	avail_ae_cycles *= adf_rl_get_num_svc_aes(accel_dev, svc_type);

	do_div(avail_ae_cycles, device_data->scan_interval);



	sla_val *= device_data->max_tp[svc_type];