Commit a9556637 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: move rawclk from runtime to display runtime info 

It's mostly about display, so move it under display. This should also
fix rawclk freq initialization in the xe driver.

v2: Change the init location

Link: https://lore.kernel.org/r/20240819133138.147511-2-maarten.lankhorst@linux.intel.com


Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/39330d09c48509e013f01fd0247a9b7c291173e2.1724144570.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent fbc64aaf

drivers/gpu/drm/i915/display/intel_backlight.c

+5 −5
Original line number Diff line number Diff line
@@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
{

	struct drm_i915_private *i915 = to_i915(connector->base.dev);



	return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),

	return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),

				 pwm_freq_hz);

}
@@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
{

	struct drm_i915_private *i915 = to_i915(connector->base.dev);



	return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),

	return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),

				 pwm_freq_hz * 128);

}
@@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
	int clock;



	if (IS_PINEVIEW(i915))

		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);

		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);

	else

		clock = KHz(i915->display.cdclk.hw.cdclk);
@@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
	int clock;



	if (IS_G4X(i915))

		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);

		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);

	else

		clock = KHz(i915->display.cdclk.hw.cdclk);
@@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
			clock = MHz(25);

		mul = 16;

	} else {

		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);

		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);

		mul = 128;

	}

drivers/gpu/drm/i915/display/intel_display_device.c

+5 −0
Original line number Diff line number Diff line
@@ -1474,6 +1474,9 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 
		}

	}



	display_runtime->rawclk_freq = intel_read_rawclk(i915);

	drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq);



	return;



display_fused_off:
@@ -1516,6 +1519,8 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf 
	drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));

	drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));

	drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));



	drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);

}



/*

drivers/gpu/drm/i915/display/intel_display_device.h

+2 −0
Original line number Diff line number Diff line
@@ -204,6 +204,8 @@ struct intel_display_runtime_info { 
		u16 step;

	} ip;



	u32 rawclk_freq;



	u8 pipe_mask;

	u8 cpu_transcoder_mask;

	u16 port_mask;

drivers/gpu/drm/i915/display/intel_display_power_well.c

+2 −2
Original line number Diff line number Diff line
@@ -1176,9 +1176,9 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 
		       MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);

	intel_de_write(dev_priv, CBR1_VLV, 0);



	drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);

	drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0);

	intel_de_write(dev_priv, RAWCLK_FREQ_VLV,

		       DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,

		       DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq,

					 1000));

}

drivers/gpu/drm/i915/display/intel_dp_aux.c

+2 −2
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 
	 * The clock divider is based off the hrawclk, and would like to run at

	 * 2MHz.  So, take the hrawclk value and divide by 2000 and use that

	 */

	return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000);

	return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq, 2000);

}



static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
@@ -103,7 +103,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 
	if (dig_port->aux_ch == AUX_CH_A)

		freq = i915->display.cdclk.hw.cdclk;

	else

		freq = RUNTIME_INFO(i915)->rawclk_freq;

		freq = DISPLAY_RUNTIME_INFO(i915)->rawclk_freq;

	return DIV_ROUND_CLOSEST(freq, 2000);

}