Commit a9650b7f authored by Ilkka Koskinen's avatar Ilkka Koskinen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events arm64: Add AmpereOne core PMU events 



Add JSON files for AmpereOne core PMU events.

Reviewed-by: default avatarJohn Garry <john.g.garry@oracle.com>
Signed-off-by: default avatarDoug Rady <dcrady@os.amperecomputing.com>
Signed-off-by: default avatarIlkka Koskinen <ilkka@os.amperecomputing.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20230427223220.1068356-1-ilkka@os.amperecomputing.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 40bf1cb0

tools/perf/pmu-events/arch/arm64/ampere/ampereone/branch.json

0 → 100644
+17 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "BR_IMMED_SPEC"

    },

    {

        "ArchStdEvent": "BR_RETURN_SPEC"

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC"

    },

    {

        "ArchStdEvent": "BR_MIS_PRED"

    },

    {

        "ArchStdEvent": "BR_PRED"

    }

]

tools/perf/pmu-events/arch/arm64/ampere/ampereone/bus.json

0 → 100644
+32 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "CPU_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_SHARED"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NOT_SHARED"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NORMAL"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_PERIPH"

    },

    {

        "ArchStdEvent": "BUS_ACCESS"

    },

    {

        "ArchStdEvent": "CNT_CYCLES"

    }

]

tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json

0 → 100644
+104 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L1D_TLB"

    },

    {

        "ArchStdEvent": "L1I_TLB"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L2I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L2D_TLB"

    },

    {

        "ArchStdEvent": "L2I_TLB"

    },

    {

        "ArchStdEvent": "DTLB_WALK"

    },

    {

        "ArchStdEvent": "ITLB_WALK"

    },

    {

        "ArchStdEvent": "L1D_CACHE_LMISS_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_LMISS"

    },

    {

        "ArchStdEvent": "L1I_CACHE_LMISS"

    },

    {

        "ArchStdEvent": "L2D_CACHE_LMISS_RD"

    }

]

tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json

0 → 100644
+698 −0

File added.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/arm64/ampere/ampereone/exception.json

0 → 100644
+44 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "EXC_UNDEF"

    },

    {

        "ArchStdEvent": "EXC_SVC"

    },

    {

        "ArchStdEvent": "EXC_PABORT"

    },

    {

        "ArchStdEvent": "EXC_DABORT"

    },

    {

        "ArchStdEvent": "EXC_IRQ"

    },

    {

        "ArchStdEvent": "EXC_FIQ"

    },

    {

        "ArchStdEvent": "EXC_HVC"

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER"

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ"

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ"

    },

    {

        "ArchStdEvent": "EXC_TAKEN"

    },

    {

        "ArchStdEvent": "EXC_RETURN"

    }

]