Commit a96e384c authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
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drm/amd/display: Initialize DP ref clk with the correct clock 



Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarRoman Li <roman.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7315a4fb

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

+2 −2
Original line number Diff line number Diff line
@@ -131,8 +131,8 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) 
	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	int dprefclk_wdivider;

	int dprefclk_src_sel;

	int dp_ref_clk_khz;

	int target_div = 600000;

	int dp_ref_clk_khz = 600000;

	int target_div;



	/* ASSERT DP Reference Clock source is from DFS*/

	REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);