Commit a9962fb8 authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: Separate HUBP surface size and rotation/mirror programming 



Separate HUBP surface size and rotation/mirror programming so that
HUBP revision without mirror/rotation do not access those register
fields.

Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 013fc06e

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c

+15 −8
Original line number Diff line number Diff line
@@ -152,16 +152,14 @@ void hubp1_program_tiling( 
			PIPE_ALIGNED, info->gfx9.pipe_aligned);

}



void hubp1_program_size_and_rotation(

void hubp1_program_size(

	struct hubp *hubp,

	enum dc_rotation_angle rotation,

	enum surface_pixel_format format,

	const union plane_size *plane_size,

	struct dc_plane_dcc_param *dcc,

	bool horizontal_mirror)

	struct dc_plane_dcc_param *dcc)

{

	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

	uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror;

	uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;



	/* Program data and meta surface pitch (calculation from addrlib)

	 * 444 or 420 luma
@@ -192,13 +190,22 @@ void hubp1_program_size_and_rotation( 
	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

		REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,

			PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);

}



void hubp1_program_rotation(

	struct hubp *hubp,

	enum dc_rotation_angle rotation,

	bool horizontal_mirror)

{

	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

	uint32_t mirror;





	if (horizontal_mirror)

		mirror = 1;

	else

		mirror = 0;





	/* Program rotation angle and horz mirror - no mirror */

	if (rotation == ROTATION_ANGLE_0)

		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
@@ -481,8 +488,8 @@ void hubp1_program_surface_config( 
{

	hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);

	hubp1_program_tiling(hubp, tiling_info, format);

	hubp1_program_size_and_rotation(

			hubp, rotation, format, plane_size, dcc, horizontal_mirror);

	hubp1_program_size(hubp, format, plane_size, dcc);

	hubp1_program_rotation(hubp, rotation, horizontal_mirror);

	hubp1_program_pixel_format(hubp, format);

}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h

+8 −5
Original line number Diff line number Diff line
@@ -268,8 +268,6 @@ 
	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\

	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\

	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\

	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\

	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\

	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\

	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\

	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
@@ -388,6 +386,8 @@ 
#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\

	HUBP_MASK_SH_LIST_DCN(mask_sh),\

	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\

	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\

	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\

	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\

	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\

	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
@@ -679,12 +679,15 @@ void hubp1_program_pixel_format( 
	struct hubp *hubp,

	enum surface_pixel_format format);



void hubp1_program_size_and_rotation(

void hubp1_program_size(

	struct hubp *hubp,

	enum dc_rotation_angle rotation,

	enum surface_pixel_format format,

	const union plane_size *plane_size,

	struct dc_plane_dcc_param *dcc,

	struct dc_plane_dcc_param *dcc);



void hubp1_program_rotation(

	struct hubp *hubp,

	enum dc_rotation_angle rotation,

	bool horizontal_mirror);



void hubp1_program_tiling(