Commit a9ae475c authored by Christophe Kerello's avatar Christophe Kerello Committed by Miquel Raynal
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mtd: rawnand: stm32_fmc2: use dma_get_slave_caps to get DMA max burst 



Use dma_get_slave_caps API to get the max burst size of a DMA channel.

For MP1 SoCs, MDMA is used and the max burst size is 128.
For MP25 SoC, DMA3 is used and the max burst size is 64.

Signed-off-by: default avatarChristophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20240219140505.85794-3-christophe.kerello@foss.st.com
parent c1e04ab4

drivers/mtd/nand/raw/stm32_fmc2_nand.c

+24 −5
Original line number Diff line number Diff line
@@ -264,6 +264,8 @@ struct stm32_fmc2_nfc { 
	struct sg_table dma_ecc_sg;

	u8 *ecc_buf;

	int dma_ecc_len;

	u32 tx_dma_max_burst;

	u32 rx_dma_max_burst;



	struct completion complete;

	struct completion dma_data_complete;
@@ -347,20 +349,26 @@ static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr) 
	stm32_fmc2_nfc_setup(chip);

	stm32_fmc2_nfc_timings_init(chip);



	if (nfc->dma_tx_ch && nfc->dma_rx_ch) {

	if (nfc->dma_tx_ch) {

		memset(&dma_cfg, 0, sizeof(dma_cfg));

		dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel];

		dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel];

		dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;

		dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;

		dma_cfg.src_maxburst = 32;

		dma_cfg.dst_maxburst = 32;

		dma_cfg.dst_maxburst = nfc->tx_dma_max_burst /

				       dma_cfg.dst_addr_width;



		ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg);

		if (ret) {

			dev_err(nfc->dev, "tx DMA engine slave config failed\n");

			return ret;

		}

	}



	if (nfc->dma_rx_ch) {

		memset(&dma_cfg, 0, sizeof(dma_cfg));

		dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel];

		dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;

		dma_cfg.src_maxburst = nfc->rx_dma_max_burst /

				       dma_cfg.src_addr_width;



		ret = dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg);

		if (ret) {
@@ -1545,6 +1553,7 @@ static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, 


static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc)

{

	struct dma_slave_caps caps;

	int ret = 0;



	nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx");
@@ -1557,6 +1566,11 @@ static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) 
		goto err_dma;

	}



	ret = dma_get_slave_caps(nfc->dma_tx_ch, &caps);

	if (ret)

		return ret;

	nfc->tx_dma_max_burst = caps.max_burst;



	nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx");

	if (IS_ERR(nfc->dma_rx_ch)) {

		ret = PTR_ERR(nfc->dma_rx_ch);
@@ -1567,6 +1581,11 @@ static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) 
		goto err_dma;

	}



	ret = dma_get_slave_caps(nfc->dma_rx_ch, &caps);

	if (ret)

		return ret;

	nfc->rx_dma_max_burst = caps.max_burst;



	nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc");

	if (IS_ERR(nfc->dma_ecc_ch)) {

		ret = PTR_ERR(nfc->dma_ecc_ch);