Commit a9b7c84d authored by Marek Vasut's avatar Marek Vasut Committed by Abel Vesa
Browse files

clk: imx8mp: Fix clkout1/2 support 



The CLKOUTn may be fed from PLL1/2/3, but the PLL1/2/3 has to be enabled
first by setting PLL_CLKE bit 11 in CCM_ANALOG_SYS_PLLn_GEN_CTRL register.
The CCM_ANALOG_SYS_PLLn_GEN_CTRL bit 11 is modeled by plln_out clock. Fix
the clock tree and place the clkout1/2 under plln_sel instead of plain plln
to let the clock subsystem correctly control the bit 11 and enable the PLL
in case the CLKOUTn is supplied by PLL1/2/3.

Fixes: 43896f56 ("clk: imx8mp: add clkout1/2 support")
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20241112013718.333771-1-marex@denx.de


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent 40384c84

drivers/clk/imx/clk-imx8mp.c

+3 −2
Original line number Diff line number Diff line
@@ -399,8 +399,9 @@ static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_r 


static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",

						  "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",

						  "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",

						  "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};

						  "arm_pll_out", "sys_pll1_out", "sys_pll2_out",

						  "sys_pll3_out", "dummy", "dummy", "osc_24m",

						  "dummy", "osc_32k"};



static struct clk_hw **hws;

static struct clk_hw_onecell_data *clk_hw_data;