Commit a9d4aff6 authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: stmmac: rk: replace empty set_to_rmii() with supports_rmii 



Rather than providing a now-empty set_to_rmii() method to indicate
that RMII is supported, switch to setting ops->supports_rmii instead.

Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: default avatarMaxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de> #px30,rk3328,rk3568,rk3588
Link: https://patch.msgid.link/E1vnYxq-00000007hor-3yXt@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent d323769d

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

+24 −62
Original line number Diff line number Diff line
@@ -268,12 +268,7 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, 


#define PX30_GRF_GMAC_CON1		0x0904



static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops px30_ops = {

	.set_to_rmii = px30_set_to_rmii,

	.set_speed = rk_set_clk_mac_speed,



	.gmac_grf_reg = PX30_GRF_GMAC_CON1,
@@ -281,6 +276,8 @@ static const struct rk_gmac_ops px30_ops = { 


	.clock_grf_reg = PX30_GRF_GMAC_CON1,

	.clock.mac_speed_mask = BIT_U16(2),



	.supports_rmii = true,

};



#define RK3128_GRF_MAC_CON0	0x0168
@@ -307,13 +304,8 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 
		     RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops rk3128_ops = {

	.set_to_rgmii = rk3128_set_to_rgmii,

	.set_to_rmii = rk3128_set_to_rmii,



	.gmac_grf_reg = RK3128_GRF_MAC_CON1,

	.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
@@ -323,6 +315,8 @@ static const struct rk_gmac_ops rk3128_ops = { 
	.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),

	.clock.rmii_clk_sel_mask = BIT_U16(11),

	.clock.mac_speed_mask = BIT_U16(10),



	.supports_rmii = true,

};



#define RK3228_GRF_MAC_CON0	0x0900
@@ -410,13 +404,8 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 
		     RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops rk3288_ops = {

	.set_to_rgmii = rk3288_set_to_rgmii,

	.set_to_rmii = rk3288_set_to_rmii,



	.gmac_grf_reg = RK3288_GRF_SOC_CON1,

	.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
@@ -426,6 +415,8 @@ static const struct rk_gmac_ops rk3288_ops = { 
	.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),

	.clock.rmii_clk_sel_mask = BIT_U16(11),

	.clock.mac_speed_mask = BIT_U16(10),



	.supports_rmii = true,

};



#define RK3308_GRF_MAC_CON0		0x04a0
@@ -434,18 +425,14 @@ static const struct rk_gmac_ops rk3288_ops = { 
#define RK3308_GMAC_FLOW_CTRL		GRF_BIT(3)

#define RK3308_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)



static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops rk3308_ops = {

	.set_to_rmii = rk3308_set_to_rmii,



	.gmac_grf_reg = RK3308_GRF_MAC_CON0,

	.gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),



	.clock_grf_reg = RK3308_GRF_MAC_CON0,

	.clock.mac_speed_mask = BIT_U16(0),



	.supports_rmii = true,

};



#define RK3328_GRF_MAC_CON0	0x0900
@@ -497,10 +484,6 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 
		     RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)

{

	regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
@@ -512,7 +495,6 @@ static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 
static const struct rk_gmac_ops rk3328_ops = {

	.init = rk3328_init,

	.set_to_rgmii = rk3328_set_to_rgmii,

	.set_to_rmii = rk3328_set_to_rmii,

	.integrated_phy_powerup = rk3328_integrated_phy_powerup,

	.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
@@ -522,6 +504,8 @@ static const struct rk_gmac_ops rk3328_ops = { 
	.clock.rmii_clk_sel_mask = BIT_U16(7),

	.clock.mac_speed_mask = BIT_U16(2),



	.supports_rmii = true,



	.regs_valid = true,

	.regs = {

		0xff540000, /* gmac2io */
@@ -554,13 +538,8 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 
		     RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops rk3366_ops = {

	.set_to_rgmii = rk3366_set_to_rgmii,

	.set_to_rmii = rk3366_set_to_rmii,



	.gmac_grf_reg = RK3366_GRF_SOC_CON6,

	.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -570,6 +549,8 @@ static const struct rk_gmac_ops rk3366_ops = { 
	.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),

	.clock.rmii_clk_sel_mask = BIT_U16(3),

	.clock.mac_speed_mask = BIT_U16(7),



	.supports_rmii = true,

};



#define RK3368_GRF_SOC_CON15	0x043c
@@ -596,13 +577,8 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 
		     RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops rk3368_ops = {

	.set_to_rgmii = rk3368_set_to_rgmii,

	.set_to_rmii = rk3368_set_to_rmii,



	.gmac_grf_reg = RK3368_GRF_SOC_CON15,

	.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -612,6 +588,8 @@ static const struct rk_gmac_ops rk3368_ops = { 
	.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),

	.clock.rmii_clk_sel_mask = BIT_U16(3),

	.clock.mac_speed_mask = BIT_U16(7),



	.supports_rmii = true,

};



#define RK3399_GRF_SOC_CON5	0xc214
@@ -638,13 +616,8 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 
		     RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops rk3399_ops = {

	.set_to_rgmii = rk3399_set_to_rgmii,

	.set_to_rmii = rk3399_set_to_rmii,



	.gmac_grf_reg = RK3399_GRF_SOC_CON5,

	.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -654,6 +627,8 @@ static const struct rk_gmac_ops rk3399_ops = { 
	.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),

	.clock.rmii_clk_sel_mask = BIT_U16(3),

	.clock.mac_speed_mask = BIT_U16(7),



	.supports_rmii = true,

};



#define RK3506_GRF_SOC_CON8		0x0020
@@ -884,18 +859,15 @@ static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 
		     RK3568_GMAC_TXCLK_DLY_ENABLE);

}



static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops rk3568_ops = {

	.init = rk3568_init,

	.set_to_rgmii = rk3568_set_to_rgmii,

	.set_to_rmii = rk3568_set_to_rmii,

	.set_speed = rk_set_clk_mac_speed,



	.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),



	.supports_rmii = true,



	.regs_valid = true,

	.regs = {

		0xfe2a0000, /* gmac0 */
@@ -969,10 +941,6 @@ static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 
		     RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));

}



static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,

				       bool enable)

{
@@ -992,7 +960,6 @@ static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input 
static const struct rk_gmac_ops rk3576_ops = {

	.init = rk3576_init,

	.set_to_rgmii = rk3576_set_to_rgmii,

	.set_to_rmii = rk3576_set_to_rmii,

	.set_clock_selection = rk3576_set_clock_selection,



	.gmac_rmii_mode_mask = BIT_U16(3),
@@ -1000,6 +967,8 @@ static const struct rk_gmac_ops rk3576_ops = { 
	.clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),

	.clock.rmii_clk_sel_mask = BIT_U16(5),



	.supports_rmii = true,



	.php_grf_required = true,

	.regs_valid = true,

	.regs = {
@@ -1120,19 +1089,15 @@ static const struct rk_gmac_ops rk3588_ops = { 
#define RV1108_GMAC_FLOW_CTRL		GRF_BIT(3)

#define RV1108_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)



static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops rv1108_ops = {

	.set_to_rmii = rv1108_set_to_rmii,



	.gmac_grf_reg = RV1108_GRF_GMAC_CON0,

	.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),



	.clock_grf_reg = RV1108_GRF_GMAC_CON0,

	.clock.rmii_clk_sel_mask = BIT_U16(7),

	.clock.mac_speed_mask = BIT_U16(2),



	.supports_rmii = true,

};



#define RV1126_GRF_GMAC_CON0		0X0070
@@ -1176,17 +1141,14 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 
		     RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));

}



static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)

{

}



static const struct rk_gmac_ops rv1126_ops = {

	.set_to_rgmii = rv1126_set_to_rgmii,

	.set_to_rmii = rv1126_set_to_rmii,

	.set_speed = rk_set_clk_mac_speed,



	.gmac_grf_reg = RV1126_GRF_GMAC_CON0,

	.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),



	.supports_rmii = true,

};



static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)