Commit a9efb7e2 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers 



Write the DP2 specific VFREQ registers.

This is preparation for enabling 128b/132b SST. This path is not
reachable yet.

v2: Check for !is_hdmi (Imre)

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7d90547e9ce01642b722efca0bf81cadb754e790.1735912293.git.jani.nikula@intel.com
parent aedeed4a

drivers/gpu/drm/i915/display/intel_ddi.c

+14 −1
Original line number Diff line number Diff line
@@ -3473,8 +3473,21 @@ static void intel_ddi_enable(struct intel_atomic_state *state, 
{

	struct intel_display *display = to_intel_display(encoder);

	struct intel_crtc *pipe_crtc;

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);

	int i;



	/* 128b/132b SST */

	if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {

		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);



		intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),

			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));

		intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),

			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));

	}



	intel_ddi_enable_transcoder_func(encoder, crtc_state);



	/* Enable/Disable DP2.0 SDP split config before transcoder */
@@ -3491,7 +3504,7 @@ static void intel_ddi_enable(struct intel_atomic_state *state, 
		intel_crtc_vblank_on(pipe_crtc_state);

	}



	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

	if (is_hdmi)

		intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);

	else

		intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);