Commit aa0a9861 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/psr: clarify intel_psr_pre_plane_update() conditions 

Make the conditions easier to follow. We don't do anything for
!psr->enabled, so hoist psr->enabled check higher, avoiding all the
checks when !psr->enabled. Stop the bitwise OR abuse on booleans by
removing the temporary variable altogether.

v2: Rebase

Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com> # v1
Link: https://patchwork.freedesktop.org/patch/msgid/20250204140518.2971530-1-jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent d0fcbf81

drivers/gpu/drm/i915/display/intel_psr.c

+21 −25
Original line number Diff line number Diff line
@@ -2804,10 +2804,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, 
					     old_crtc_state->uapi.encoder_mask) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

		struct intel_psr *psr = &intel_dp->psr;

		bool needs_to_disable = false;



		mutex_lock(&psr->lock);



		if (psr->enabled) {

			/*

			 * Reasons to disable:

			 * - PSR disabled in new state
@@ -2816,22 +2816,18 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, 
			 * - Region Early Transport changing

			 * - Display WA #1136: skl, bxt

			 */

		needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);

		needs_to_disable |= !new_crtc_state->has_psr;

		needs_to_disable |= !new_crtc_state->active_planes;

		needs_to_disable |= new_crtc_state->has_sel_update != psr->sel_update_enabled;

		needs_to_disable |= new_crtc_state->enable_psr2_su_region_et !=

			psr->su_region_et_enabled;

		needs_to_disable |= new_crtc_state->has_panel_replay !=

			psr->panel_replay_enabled;

		needs_to_disable |= DISPLAY_VER(i915) < 11 &&

			new_crtc_state->wm_level_disabled;



		if (psr->enabled && needs_to_disable)

			if (intel_crtc_needs_modeset(new_crtc_state) ||

			    !new_crtc_state->has_psr ||

			    !new_crtc_state->active_planes ||

			    new_crtc_state->has_sel_update != psr->sel_update_enabled ||

			    new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled ||

			    new_crtc_state->has_panel_replay != psr->panel_replay_enabled ||

			    (DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled))

				intel_psr_disable_locked(intel_dp);

		else if (psr->enabled && new_crtc_state->wm_level_disabled)

			else if (new_crtc_state->wm_level_disabled)

				/* Wa_14015648006 */

				wm_optimization_wa(intel_dp, new_crtc_state);

		}



		mutex_unlock(&psr->lock);

	}