Commit aa0c02f0 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/vbt: add anonymous structs to group DSI VBT defs 



The grouping of DSI VBT definitions is hard to follow and match against
the spec. Use anonymous structs and add comments with the spec
description.

Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/f57ca596aefa3ef0b4ce1f36452410cf745acddd.1754925923.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent f3c65a8e

drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h

+47 −40
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ struct mipi_config { 
	u16 panel_id;



	/* General Params */

	struct {

		u32 enable_dithering:1;

		u32 rsvd1:1;

		u32 is_bridge:1;
@@ -64,14 +65,12 @@ struct mipi_config { 
#define PPS_BLC_SOC    1

		u32 pwm_blc:1;



	/* Bit 13:10 */

#define PIXEL_FORMAT_RGB565			0x1

#define PIXEL_FORMAT_RGB666			0x2

#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3

#define PIXEL_FORMAT_RGB888			0x4

		u32 videomode_color_format:4;



	/* Bit 15:14 */

#define ENABLE_ROTATION_0	0x0

#define ENABLE_ROTATION_90	0x1

#define ENABLE_ROTATION_180	0x2
@@ -79,8 +78,10 @@ struct mipi_config { 
		u32 rotation:2;

		u32 bta_enabled:1;

		u32 rsvd2:15;

	} __packed;



	/* 2 byte Port Description */

	/* Port Desc */

	struct {

#define DUAL_LINK_NOT_SUPPORTED	0

#define DUAL_LINK_FRONT_BACK	1

#define DUAL_LINK_PIXEL_ALT	2
@@ -94,6 +95,7 @@ struct mipi_config { 
		u16 dl_dcs_cabc_ports:2;

		u16 dl_dcs_backlight_ports:2;

		u16 rsvd3:4;

	} __packed;



	u16 rsvd4;
@@ -102,18 +104,22 @@ struct mipi_config { 
	u32 dsi_ddr_clk;

	u32 bridge_ref_clk;



	/* LP Byte Clock */

	struct {

#define  BYTE_CLK_SEL_20MHZ		0

#define  BYTE_CLK_SEL_10MHZ		1

#define  BYTE_CLK_SEL_5MHZ		2

		u8 byte_clk_sel:2;



		u8 rsvd6:6;

	} __packed;



	/* DPHY Flags */

	/* DPhy Flags */

	struct {

		u16 dphy_param_valid:1;

		u16 eot_pkt_disabled:1;

		u16 enable_clk_stop:1;

		u16 rsvd7:13;

	} __packed;



	u32 hs_tx_timeout;

	u32 lp_rx_timeout;
@@ -123,7 +129,8 @@ struct mipi_config { 
	u32 dbi_bw_timer;

	u32 lp_byte_clk_val;



	/*  4 byte Dphy Params */

	/*  DPhy Params */

	struct {

		u32 prepare_cnt:6;

		u32 rsvd8:2;

		u32 clk_zero_cnt:8;
@@ -131,6 +138,7 @@ struct mipi_config { 
		u32 rsvd9:3;

		u32 exit_zero_cnt:6;

		u32 rsvd10:2;

	} __packed;



	u32 clk_lane_switch_cnt;

	u32 hl_switch_cnt;
@@ -168,7 +176,6 @@ struct mipi_config { 
	u8 reset_r_n;

	u8 pwr_down_r;

	u8 stdby_r_n;



} __packed;



/* all delays have a unit of 100us */