Commit aa5d2ca7 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel: Fix bitmask of OCR and FRONTEND events for LNC



The released OCR and FRONTEND events utilized more bits on Lunar Lake
p-core. The corresponding mask in the extra_regs has to be extended to
unblock the extra bits.

Add a dedicated intel_lnc_extra_regs.

Fixes: a932aa0e ("perf/x86: Add Lunar Lake and Arrow Lake support")
Reported-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20241216160252.430858-1-kan.liang@linux.intel.com
parent b8c3a250
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+11 −1
Original line number Diff line number Diff line
@@ -429,6 +429,16 @@ static struct event_constraint intel_lnc_event_constraints[] = {
	EVENT_CONSTRAINT_END
};

static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
	INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0),
	INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1),
	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
	INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
	INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
	INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
	INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
	EVENT_EXTRA_END
};

EVENT_ATTR_STR(mem-loads,	mem_ld_nhm,	"event=0x0b,umask=0x10,ldlat=3");
EVENT_ATTR_STR(mem-loads,	mem_ld_snb,	"event=0xcd,umask=0x1,ldlat=3");
@@ -6422,7 +6432,7 @@ static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
	intel_pmu_init_glc(pmu);
	hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
	hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
	hybrid(pmu, extra_regs) = intel_rwc_extra_regs;
	hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
}

static __always_inline void intel_pmu_init_skt(struct pmu *pmu)