Commit aa8c5334 authored by Martin K. Petersen's avatar Martin K. Petersen
Browse files

Merge patch series "scsi: ufs: ufs-pci: Fix hibernate state transition for... 

Merge patch series "scsi: ufs: ufs-pci: Fix hibernate state transition for Intel MTL-like host controllers"

Adrian Hunter <adrian.hunter@intel.com> says:

Hi

Here is V2 of a couple of fixes for Intel MTL-like UFS host controllers,
related to link Hibernation state.

Following the fixes are some improvements for the enabling and disabling
of UIC Completion interrupts.

Link: https://lore.kernel.org/r/20250723165856.145750-1-adrian.hunter@intel.com



Conflicts:
	drivers/ufs/core/ufshcd.c

Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parents 60feab05 22b246e3

drivers/ufs/core/ufshcd.c

+40 −55
Original line number Diff line number Diff line
@@ -364,6 +364,34 @@ void ufshcd_disable_irq(struct ufs_hba *hba) 
}

EXPORT_SYMBOL_GPL(ufshcd_disable_irq);



/**

 * ufshcd_enable_intr - enable interrupts

 * @hba: per adapter instance

 * @intrs: interrupt bits

 */

static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)

{

	u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);

	u32 new_val = old_val | intrs;



	if (new_val != old_val)

		ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE);

}



/**

 * ufshcd_disable_intr - disable interrupts

 * @hba: per adapter instance

 * @intrs: interrupt bits

 */

static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)

{

	u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);

	u32 new_val = old_val & ~intrs;



	if (new_val != old_val)

		ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE);

}



static void ufshcd_configure_wb(struct ufs_hba *hba)

{

	if (!ufshcd_is_wb_allowed(hba))
@@ -2596,6 +2624,7 @@ __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 
 */

int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)

{

	unsigned long flags;

	int ret;



	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
@@ -2605,6 +2634,10 @@ int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 
	mutex_lock(&hba->uic_cmd_mutex);

	ufshcd_add_delay_before_dme_cmd(hba);



	spin_lock_irqsave(hba->host->host_lock, flags);

	ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);

	spin_unlock_irqrestore(hba->host->host_lock, flags);



	ret = __ufshcd_send_uic_cmd(hba, uic_cmd);

	if (!ret)

		ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
@@ -2681,32 +2714,6 @@ static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 
	return ufshcd_crypto_fill_prdt(hba, lrbp);

}



/**

 * ufshcd_enable_intr - enable interrupts

 * @hba: per adapter instance

 * @intrs: interrupt bits

 */

static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)

{

	u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);



	set |= intrs;

	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);

}



/**

 * ufshcd_disable_intr - disable interrupts

 * @hba: per adapter instance

 * @intrs: interrupt bits

 */

static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)

{

	u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);



	set &= ~intrs;

	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);

}



/**

 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request

 * descriptor according to request
@@ -4318,7 +4325,6 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 
	unsigned long flags;

	u8 status;

	int ret;

	bool reenable_intr = false;



	mutex_lock(&hba->uic_cmd_mutex);

	ufshcd_add_delay_before_dme_cmd(hba);
@@ -4329,15 +4335,7 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 
		goto out_unlock;

	}

	hba->uic_async_done = &uic_async_done;

	if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {

	ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);

		/*

		 * Make sure UIC command completion interrupt is disabled before

		 * issuing UIC command.

		 */

		ufshcd_readl(hba, REG_INTERRUPT_ENABLE);

		reenable_intr = true;

	}

	spin_unlock_irqrestore(hba->host->host_lock, flags);

	ret = __ufshcd_send_uic_cmd(hba, cmd);

	if (ret) {
@@ -4381,8 +4379,6 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 
	spin_lock_irqsave(hba->host->host_lock, flags);

	hba->active_uic_cmd = NULL;

	hba->uic_async_done = NULL;

	if (reenable_intr)

		ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);

	if (ret && !hba->pm_op_in_progress) {

		ufshcd_set_link_broken(hba);

		ufshcd_schedule_eh_work(hba);
@@ -4413,28 +4409,17 @@ int ufshcd_send_bsg_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 
{

	int ret;



	if (uic_cmd->argument1 != UIC_ARG_MIB(PA_PWRMODE) ||

	    uic_cmd->command != UIC_CMD_DME_SET)

		return ufshcd_send_uic_cmd(hba, uic_cmd);



	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)

		return 0;



	ufshcd_hold(hba);



	if (uic_cmd->argument1 == UIC_ARG_MIB(PA_PWRMODE) &&

	    uic_cmd->command == UIC_CMD_DME_SET) {

	ret = ufshcd_uic_pwr_ctrl(hba, uic_cmd);

		goto out;

	}



	mutex_lock(&hba->uic_cmd_mutex);

	ufshcd_add_delay_before_dme_cmd(hba);



	ret = __ufshcd_send_uic_cmd(hba, uic_cmd);

	if (!ret)

		ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);



	mutex_unlock(&hba->uic_cmd_mutex);



out:

	ufshcd_release(hba);



	return ret;

}

drivers/ufs/host/ufshcd-pci.c

+9 −24
Original line number Diff line number Diff line
@@ -22,17 +22,12 @@ 


#define MAX_SUPP_MAC 64



struct ufs_host {

	void (*late_init)(struct ufs_hba *hba);

};



enum intel_ufs_dsm_func_id {

	INTEL_DSM_FNS		=  0,

	INTEL_DSM_RESET		=  1,

};



struct intel_host {

	struct ufs_host ufs_host;

	u32		dsm_fns;

	u32		active_ltr;

	u32		idle_ltr;
@@ -408,8 +403,14 @@ static int ufs_intel_ehl_init(struct ufs_hba *hba) 
	return ufs_intel_common_init(hba);

}



static void ufs_intel_lkf_late_init(struct ufs_hba *hba)

static int ufs_intel_lkf_init(struct ufs_hba *hba)

{

	int err;



	hba->nop_out_timeout = 200;

	hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;

	hba->caps |= UFSHCD_CAP_CRYPTO;

	err = ufs_intel_common_init(hba);

	/* LKF always needs a full reset, so set PM accordingly */

	if (hba->caps & UFSHCD_CAP_DEEPSLEEP) {

		hba->spm_lvl = UFS_PM_LVL_6;
@@ -418,19 +419,6 @@ static void ufs_intel_lkf_late_init(struct ufs_hba *hba) 
		hba->spm_lvl = UFS_PM_LVL_5;

		hba->rpm_lvl = UFS_PM_LVL_5;

	}

}



static int ufs_intel_lkf_init(struct ufs_hba *hba)

{

	struct ufs_host *ufs_host;

	int err;



	hba->nop_out_timeout = 200;

	hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;

	hba->caps |= UFSHCD_CAP_CRYPTO;

	err = ufs_intel_common_init(hba);

	ufs_host = ufshcd_get_variant(hba);

	ufs_host->late_init = ufs_intel_lkf_late_init;

	return err;

}
@@ -444,6 +432,8 @@ static int ufs_intel_adl_init(struct ufs_hba *hba) 


static int ufs_intel_mtl_init(struct ufs_hba *hba)

{

	hba->rpm_lvl = UFS_PM_LVL_2;

	hba->spm_lvl = UFS_PM_LVL_2;

	hba->caps |= UFSHCD_CAP_CRYPTO | UFSHCD_CAP_WB_EN;

	return ufs_intel_common_init(hba);

}
@@ -574,7 +564,6 @@ static void ufshcd_pci_remove(struct pci_dev *pdev) 
static int

ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)

{

	struct ufs_host *ufs_host;

	struct ufs_hba *hba;

	void __iomem *mmio_base;

	int err;
@@ -607,10 +596,6 @@ ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
		return err;

	}



	ufs_host = ufshcd_get_variant(hba);

	if (ufs_host && ufs_host->late_init)

		ufs_host->late_init(hba);



	pm_runtime_put_noidle(&pdev->dev);

	pm_runtime_allow(&pdev->dev);