Commit aabb7075 authored by Felipe Balbi's avatar Felipe Balbi Committed by Greg Kroah-Hartman
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usb: dwc3: gadget: allow clock gating to work 



The dwc3 core has internal clock gating support.

Let's allow that to happen by clearing the disable
bit in GCTL register.

Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 26ceca97

drivers/usb/dwc3/core.h

+6 −0
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ 
#define DWC3_GCTL_CORESOFTRESET	(1 << 11)

#define DWC3_GCTL_SCALEDOWN(n)	(n << 4)

#define DWC3_GCTL_DISSCRAMBLE	(1 << 3)

#define DWC3_GCTL_DSBLCLKGTNG	(1 << 0)



/* Global USB2 PHY Configuration Register */

#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
@@ -170,6 +171,11 @@ 
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)

#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)



/* Global HWPARAMS1 Register */

#define DWC3_GHWPARAMS1_EN_PWROPT(n)	((n & (3 << 24)) >> 24)

#define DWC3_GHWPARAMS1_EN_PWROPT_NO	0

#define DWC3_GHWPARAMS1_EN_PWROPT_CLK	1



/* Device Configuration Register */

#define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)

#define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)

drivers/usb/dwc3/gadget.c

+8 −0
Original line number Diff line number Diff line
@@ -1164,6 +1164,14 @@ static int dwc3_gadget_start(struct usb_gadget *g, 
	reg &= ~DWC3_GCTL_DISSCRAMBLE;

	reg |= DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE);



	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams0)) {

	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:

		reg &= ~DWC3_GCTL_DSBLCLKGTNG;

		break;

	default:

		dev_dbg(dwc->dev, "No power optimization available\n");

	}



	/*

	 * WORKAROUND: DWC3 revisions <1.90a have a bug

	 * when The device fails to connect at SuperSpeed