Commit aacad391 authored by Svyatoslav Ryhel's avatar Svyatoslav Ryhel Committed by Greg Kroah-Hartman
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usb: phy: tegra: cosmetic fixes 



Change TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC to its literal value instead of
using the BIT macro, as it is an enumeration. Correct the spelling in the
comment and rename uhsic_registers_shift to uhsic_registers_offset.
These changes are cosmetic and do not affect code behavior.

Signed-off-by: default avatarSvyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Link: https://patch.msgid.link/20260202080526.23487-2-clamor95@gmail.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 8ccfe3ac

drivers/usb/phy/phy-tegra-usb.c

+6 −6
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ 
#define TEGRA_USB_HOSTPC1_DEVLC			0x1b4

#define   TEGRA_USB_HOSTPC1_DEVLC_PTS(x)	(((x) & 0x7) << 29)

#define   TEGRA_USB_HOSTPC1_DEVLC_PHCD		BIT(22)

#define   TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC	BIT(2)

#define   TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC	4



/* Bits of PORTSC1, which will get cleared by writing 1 into them */

#define TEGRA_PORTSC1_RWC_BITS	(PORT_CSC | PORT_PEC | PORT_OCC)
@@ -169,7 +169,7 @@ 
/*

 * Tegra20 has no UTMIP registers on PHY2 and UHSIC registers start from 0x800

 * just where UTMIP registers should have been. This is the case only with Tegra20

 * Tegra30+ have UTMIP registers at 0x800 and UHSIC registers shifter by 0x400

 * Tegra30+ have UTMIP registers at 0x800 and UHSIC registers are shifted by 0x400

 * to 0xc00, but register layout is preserved.

 */

#define UHSIC_PLL_CFG1				0x804
@@ -873,7 +873,7 @@ static int ulpi_phy_power_off(struct tegra_usb_phy *phy) 
static u32 tegra_hsic_readl(struct tegra_usb_phy *phy, u32 reg)

{

	void __iomem *base = phy->regs;

	u32 shift = phy->soc_config->uhsic_registers_shift;

	u32 shift = phy->soc_config->uhsic_registers_offset;



	return readl_relaxed(base + shift + reg);

}
@@ -881,7 +881,7 @@ static u32 tegra_hsic_readl(struct tegra_usb_phy *phy, u32 reg) 
static void tegra_hsic_writel(struct tegra_usb_phy *phy, u32 reg, u32 value)

{

	void __iomem *base = phy->regs;

	u32 shift = phy->soc_config->uhsic_registers_shift;

	u32 shift = phy->soc_config->uhsic_registers_offset;



	writel_relaxed(value, base + shift + reg);

}
@@ -1469,7 +1469,7 @@ static const struct tegra_phy_soc_config tegra20_soc_config = { 
	.requires_usbmode_setup = false,

	.requires_extra_tuning_parameters = false,

	.requires_pmc_ao_power_up = false,

	.uhsic_registers_shift = 0,

	.uhsic_registers_offset = 0,

	.uhsic_tx_rtune = 0, /* 40 ohm */

};
@@ -1479,7 +1479,7 @@ static const struct tegra_phy_soc_config tegra30_soc_config = { 
	.requires_usbmode_setup = true,

	.requires_extra_tuning_parameters = true,

	.requires_pmc_ao_power_up = true,

	.uhsic_registers_shift = 0x400,

	.uhsic_registers_offset = 0x400,

	.uhsic_tx_rtune = 8,  /* 50 ohm */

};

include/linux/usb/tegra_usb_phy.h

+2 −2
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ struct gpio_desc; 
 * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level

 *      and hsdiscon_level should be set for adequate signal quality

 * requires_pmc_ao_power_up: true if USB AO is powered down by default

 * uhsic_registers_shift: for Tegra30+ where HSIC registers were shifted

 * uhsic_registers_offset: for Tegra30+ where HSIC registers were offset

 *      comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2

 * uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS driver

 */
@@ -34,7 +34,7 @@ struct tegra_phy_soc_config { 
	bool requires_usbmode_setup;

	bool requires_extra_tuning_parameters;

	bool requires_pmc_ao_power_up;

	u32 uhsic_registers_shift;

	u32 uhsic_registers_offset;

	u32 uhsic_tx_rtune;

};