Commit aae0594a authored by Li Ming's avatar Li Ming Committed by Dave Jiang
Browse files

cxl/region: Fix the first aliased address miscalculation 



In extended linear cache(ELC) case, cxl_port_get_spa_cache_alias() helps
to get the aliased address of a SPA, it considers the first address in
CXL memory range is "region start + region cache size + 1", but it
should be "region start + region cache size".

So if a SPA is equal to "region start + region cache size", its aliased
address should be "SPA - region cache size".

Signed-off-by: default avatarLi Ming <ming.li@zohomail.com>
Reviewed-by: default avatarAlison Schofield <alison.schofield@intel.com>
Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20250317070124.815028-1-ming.li@zohomail.com


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 3b5d4324

drivers/cxl/core/region.c

+1 −1
Original line number Diff line number Diff line
@@ -3460,7 +3460,7 @@ u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa) 
			if (!p->cache_size)

				return ~0ULL;



			if (spa > p->res->start + p->cache_size)

			if (spa >= p->res->start + p->cache_size)

				return spa - p->cache_size;



			return spa + p->cache_size;