Commit aaf00e61 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2024-04-10' of... 

Merge tag 'drm-intel-fixes-2024-04-10' of https://anongit.freedesktop.org/git/drm/drm-intel

 into drm-fixes

Display fixes:
- Couple CDCLK programming fixes (Ville)
- HDCP related fix (Suraj)
- 4 Bigjoiner related fixes (Ville)

Core fix:
- Fix for a circular locking around GuC on reset+wedged case (John)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZhcJxlzc6zLMC1c-@intel.com
parents 718c4fb2 dcd8992e

drivers/gpu/drm/i915/display/intel_cdclk.c

+31 −11
Original line number Diff line number Diff line
@@ -2534,7 +2534,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 
		intel_atomic_get_old_cdclk_state(state);

	const struct intel_cdclk_state *new_cdclk_state =

		intel_atomic_get_new_cdclk_state(state);

	enum pipe pipe = new_cdclk_state->pipe;

	struct intel_cdclk_config cdclk_config;

	enum pipe pipe;



	if (!intel_cdclk_changed(&old_cdclk_state->actual,

				 &new_cdclk_state->actual))
@@ -2543,12 +2544,25 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 
	if (IS_DG2(i915))

		intel_cdclk_pcode_pre_notify(state);



	if (pipe == INVALID_PIPE ||

	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {

		drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);

	if (new_cdclk_state->disable_pipes) {

		cdclk_config = new_cdclk_state->actual;

		pipe = INVALID_PIPE;

	} else {

		if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {

			cdclk_config = new_cdclk_state->actual;

			pipe = new_cdclk_state->pipe;

		} else {

			cdclk_config = old_cdclk_state->actual;

			pipe = INVALID_PIPE;

		}



		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);

		cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,

						 old_cdclk_state->actual.voltage_level);

	}



	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);



	intel_set_cdclk(i915, &cdclk_config, pipe);

}



/**
@@ -2566,7 +2580,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 
		intel_atomic_get_old_cdclk_state(state);

	const struct intel_cdclk_state *new_cdclk_state =

		intel_atomic_get_new_cdclk_state(state);

	enum pipe pipe = new_cdclk_state->pipe;

	enum pipe pipe;



	if (!intel_cdclk_changed(&old_cdclk_state->actual,

				 &new_cdclk_state->actual))
@@ -2575,13 +2589,16 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 
	if (IS_DG2(i915))

		intel_cdclk_pcode_post_notify(state);



	if (pipe != INVALID_PIPE &&

	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {

	if (!new_cdclk_state->disable_pipes &&

	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)

		pipe = new_cdclk_state->pipe;

	else

		pipe = INVALID_PIPE;



	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);



	intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);

}

}



static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)

{
@@ -3058,6 +3075,7 @@ static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_globa 
		return NULL;



	cdclk_state->pipe = INVALID_PIPE;

	cdclk_state->disable_pipes = false;



	return &cdclk_state->base;

}
@@ -3236,6 +3254,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 
		if (ret)

			return ret;



		new_cdclk_state->disable_pipes = true;



		drm_dbg_kms(&dev_priv->drm,

			    "Modeset required for cdclk change\n");

	}

drivers/gpu/drm/i915/display/intel_cdclk.h

+3 −0
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ struct intel_cdclk_state { 


	/* bitmask of active pipes */

	u8 active_pipes;



	/* update cdclk with pipes disabled */

	bool disable_pipes;

};



int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

+5 −0
Original line number Diff line number Diff line
@@ -4256,7 +4256,12 @@ static bool m_n_equal(const struct intel_link_m_n *m_n_1, 
static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,

				       const struct intel_crtc_state *crtc_state2)

{

	/*

	 * FIXME the modeset sequence is currently wrong and

	 * can't deal with bigjoiner + port sync at the same time.

	 */

	return crtc_state1->hw.active && crtc_state2->hw.active &&

		!crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes &&

		crtc_state1->output_types == crtc_state2->output_types &&

		crtc_state1->output_format == crtc_state2->output_format &&

		crtc_state1->lane_count == crtc_state2->lane_count &&

drivers/gpu/drm/i915/display/intel_dp.c

+5 −1
Original line number Diff line number Diff line
@@ -2725,7 +2725,11 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, 
		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);

	int pixel_clock;



	if (has_seamless_m_n(connector))

	/*

	 * FIXME all joined pipes share the same transcoder.

	 * Need to account for that when updating M/N live.

	 */

	if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes)

		pipe_config->update_m_n = true;



	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

+4 −1
Original line number Diff line number Diff line
@@ -691,12 +691,15 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector, 
	u8 bcaps;

	int ret;



	*hdcp_capable = false;

	*hdcp2_capable = false;

	if (!intel_encoder_is_mst(connector->encoder))

		return -EINVAL;



	ret =  _intel_dp_hdcp2_get_capability(aux, hdcp2_capable);

	if (ret)

		return ret;

		drm_dbg_kms(&i915->drm,

			    "HDCP2 DPCD capability read failed err: %d\n", ret);



	ret = intel_dp_hdcp_read_bcaps(aux, i915, &bcaps);

	if (ret)