Commit ab0e1314 authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
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clk: qcom: camcc-sm6350: Fix PLL config of PLL2 



The 'Agera' PLLs (with clk_agera_pll_configure) do not take some of the
parameters that are provided in the vendor driver. Instead the upstream
configuration should provide the final user_ctl value that is written to
the USER_CTL register.

Fix the config so that the PLL is configured correctly, and fixes
CAMCC_MCLK* being stuck off.

Fixes: 80f5451d ("clk: qcom: Add camera clock controller driver for SM6350")
Suggested-by: default avatarTaniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Reviewed-by: default avatarTaniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251021-agera-pll-fixups-v1-1-8c1d8aff4afc@fairphone.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent fd0b632e

drivers/clk/qcom/camcc-sm6350.c

+1 −5
Original line number Diff line number Diff line
@@ -145,15 +145,11 @@ static struct clk_alpha_pll_postdiv camcc_pll1_out_even = { 
static const struct alpha_pll_config camcc_pll2_config = {

	.l = 0x64,

	.alpha = 0x0,

	.post_div_val = 0x3 << 8,

	.post_div_mask = 0x3 << 8,

	.aux_output_mask = BIT(1),

	.main_output_mask = BIT(0),

	.early_output_mask = BIT(3),

	.config_ctl_val = 0x20000800,

	.config_ctl_hi_val = 0x400003d2,

	.test_ctl_val = 0x04000400,

	.test_ctl_hi_val = 0x00004000,

	.user_ctl_val = 0x0000030b,

};



static struct clk_alpha_pll camcc_pll2 = {