Commit ab1ad455 authored by Georgi Vlaev's avatar Georgi Vlaev Committed by Vignesh Raghavendra
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arm64: dts: ti: k3-am62-main: Add epwm nodes



Add the compatible DT nodes for all EPWM instances
present in AM62 SoC. There is a total of 3 EPWM modules
available, sharing the same K3 IP as in AM64 SoC.

This also adds a required "ti,am62-epwm-tbclk" clock
provider node for the EPWM time-base clock.

Signed-off-by: default avatarGeorgi Vlaev <g-vlaev@ti.com>
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20220531205229.198011-2-g-vlaev@ti.com
parent b216dc1a
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+33 −0
Original line number Diff line number Diff line
@@ -54,6 +54,12 @@ phy_gmii_sel: phy@4044 {
			reg = <0x4044 0x8>;
			#phy-cells = <1>;
		};

		epwm_tbclk: clock@4130 {
			compatible = "ti,am62-epwm-tbclk", "syscon";
			reg = <0x4130 0x4>;
			#clock-cells = <1>;
		};
	};

	dmss: bus@48000000 {
@@ -584,4 +590,31 @@ main_mcan0: can@20701000 {
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	epwm0: pwm@23000000 {
		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x23000000 0x00 0x100>;
		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
		clock-names = "tbclk", "fck";
	};

	epwm1: pwm@23010000 {
		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x23010000 0x00 0x100>;
		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
		clock-names = "tbclk", "fck";
	};

	epwm2: pwm@23020000 {
		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x23020000 0x00 0x100>;
		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
		clock-names = "tbclk", "fck";
	};
};