Commit ab4219db authored by Dragos Tatulea's avatar Dragos Tatulea Committed by Jakub Kicinski
Browse files

net/mlx5e: SHAMPO, Rework header allocation loop 



The current loop code was based on the assumption
that there can be page leftovers from previous function calls.

This patch changes the allocation loop to make it clearer how
pages get allocated every MLX5E_SHAMPO_WQ_HEADER_PER_PAGE headers.
This change has no functional implications.

Signed-off-by: default avatarDragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20241107194357.683732-13-tariqt@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 945ca432

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

+17 −15
Original line number Diff line number Diff line
@@ -666,8 +666,7 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *rq, 
	u16 pi, header_offset, err, wqe_bbs;

	u32 lkey = rq->mdev->mlx5e_res.hw_objs.mkey;

	struct mlx5e_umr_wqe *umr_wqe;

	int headroom, i;

	u64 addr = 0;

	int headroom, i = 0;



	headroom = rq->buff.headroom;

	wqe_bbs = MLX5E_KSM_UMR_WQEBBS(ksm_entries);
@@ -676,23 +675,26 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *rq, 
	build_ksm_umr(sq, umr_wqe, shampo->key, index, ksm_entries);



	WARN_ON_ONCE(ksm_entries & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1));

	for (i = 0; i < ksm_entries; i++, index++) {

		header_offset = mlx5e_shampo_hd_offset(index);

		if (!header_offset) {

	while (i < ksm_entries) {

		struct mlx5e_frag_page *frag_page = mlx5e_shampo_hd_to_frag_page(rq, index);

		u64 addr;



		err = mlx5e_page_alloc_fragmented(rq, frag_page);

		if (unlikely(err))

			goto err_unmap;





		addr = page_pool_get_dma_addr(frag_page->page);

		}



		umr_wqe->inline_ksms[i] = (struct mlx5_ksm) {

		for (int j = 0; j < MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; j++) {

			header_offset = mlx5e_shampo_hd_offset(index++);



			umr_wqe->inline_ksms[i++] = (struct mlx5_ksm) {

				.key = cpu_to_be32(lkey),

				.va  = cpu_to_be64(addr + header_offset + headroom),

			};

		}

	}



	sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) {

		.wqe_type	= MLX5E_ICOSQ_WQE_SHAMPO_HD_UMR,