Commit ab499990 authored by Thorsten Blum's avatar Thorsten Blum Committed by Dinh Nguyen
Browse files

clk: socfpga: clk-pll: Optimize local variables 



Since readl() returns a u32, the local variables reg and bypass can also
have the data type u32. Furthermore, divf and divq are derived from reg
and can also be a u32.

Since do_div() casts the divisor to u32 anyway, changing the data type
of divq to u32 removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:

  WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead

Compile-tested only.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarThorsten Blum <thorsten.blum@linux.dev>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 0af2f6be

drivers/clk/socfpga/clk-pll.c

+2 −2
Original line number Diff line number Diff line
@@ -39,9 +39,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, 
					 unsigned long parent_rate)

{

	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);

	unsigned long divf, divq, reg;

	u32 divf, divq, reg;

	unsigned long long vco_freq;

	unsigned long bypass;

	u32 bypass;



	reg = readl(socfpgaclk->hw.reg);

	bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);