Commit aba59ce1 authored by Iwona Winiarska's avatar Iwona Winiarska
Browse files

peci: aspeed: Clear clock_divider value before setting it 



PECI clock divider is programmed on 10:8 bits of PECI Control register.
Before setting a new value, clear bits read from hardware.

Reviewed-by: default avatarBilly Tsai <billy_tsai@aspeedtech.com>
Link: https://lore.kernel.org/r/20240417134849.5793-1-iwona.winiarska@intel.com


Signed-off-by: default avatarIwona Winiarska <iwona.winiarska@intel.com>
parent a43b9ec0

drivers/peci/controller/peci-aspeed.c

+1 −0
Original line number Diff line number Diff line
@@ -351,6 +351,7 @@ static int clk_aspeed_peci_set_rate(struct clk_hw *hw, unsigned long rate, 
	clk_aspeed_peci_find_div_values(this_rate, &msg_timing, &clk_div_exp);



	val = readl(aspeed_peci->base + ASPEED_PECI_CTRL);

	val &= ~ASPEED_PECI_CTRL_CLK_DIV_MASK;

	val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, clk_div_exp);

	writel(val, aspeed_peci->base + ASPEED_PECI_CTRL);