Loading include/asm-x86/msr.h +42 −39 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ static inline unsigned long long native_read_tscp(unsigned int *aux) */ #ifdef CONFIG_X86_64 #define DECLARE_ARGS(val, low, high) unsigned low, high #define EAX_EDX_VAL(val, low, high) (low | ((u64)(high) << 32)) #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) #else Loading Loading @@ -118,7 +118,7 @@ static inline unsigned long long native_read_pmc(int counter) #define rdmsr(msr, val1, val2) \ do { \ u64 __val = native_read_msr(msr); \ u64 __val = native_read_msr((msr)); \ (val1) = (u32)__val; \ (val2) = (u32)(__val >> 32); \ } while (0) Loading @@ -129,10 +129,10 @@ static inline void wrmsr(unsigned msr, unsigned low, unsigned high) } #define rdmsrl(msr, val) \ ((val) = native_read_msr(msr)) ((val) = native_read_msr((msr))) #define wrmsrl(msr, val) \ native_write_msr(msr, (u32)((u64)(val)), (u32)((u64)(val) >> 32)) native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) /* wrmsr with exception handling */ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) Loading @@ -144,7 +144,7 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) #define rdmsr_safe(msr, p1, p2) \ ({ \ int __err; \ u64 __val = native_read_msr_safe(msr, &__err); \ u64 __val = native_read_msr_safe((msr), &__err); \ (*p1) = (u32)__val; \ (*p2) = (u32)(__val >> 32); \ __err; \ Loading @@ -158,7 +158,7 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) #define rdpmc(counter, low, high) \ do { \ u64 _l = native_read_pmc(counter); \ u64 _l = native_read_pmc((counter)); \ (low) = (u32)_l; \ (high) = (u32)(_l >> 32); \ } while (0) Loading @@ -175,16 +175,18 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) #endif /* !CONFIG_PARAVIRT */ #define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32)) #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ (u32)((val) >> 32)) #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2)) #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0) #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0) #ifdef CONFIG_SMP void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); #else /* CONFIG_SMP */ static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) Loading @@ -195,7 +197,8 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) { wrmsr(msr_no, l, h); } static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) { return rdmsr_safe(msr_no, l, h); } Loading Loading
include/asm-x86/msr.h +42 −39 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ static inline unsigned long long native_read_tscp(unsigned int *aux) */ #ifdef CONFIG_X86_64 #define DECLARE_ARGS(val, low, high) unsigned low, high #define EAX_EDX_VAL(val, low, high) (low | ((u64)(high) << 32)) #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) #else Loading Loading @@ -118,7 +118,7 @@ static inline unsigned long long native_read_pmc(int counter) #define rdmsr(msr, val1, val2) \ do { \ u64 __val = native_read_msr(msr); \ u64 __val = native_read_msr((msr)); \ (val1) = (u32)__val; \ (val2) = (u32)(__val >> 32); \ } while (0) Loading @@ -129,10 +129,10 @@ static inline void wrmsr(unsigned msr, unsigned low, unsigned high) } #define rdmsrl(msr, val) \ ((val) = native_read_msr(msr)) ((val) = native_read_msr((msr))) #define wrmsrl(msr, val) \ native_write_msr(msr, (u32)((u64)(val)), (u32)((u64)(val) >> 32)) native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) /* wrmsr with exception handling */ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) Loading @@ -144,7 +144,7 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) #define rdmsr_safe(msr, p1, p2) \ ({ \ int __err; \ u64 __val = native_read_msr_safe(msr, &__err); \ u64 __val = native_read_msr_safe((msr), &__err); \ (*p1) = (u32)__val; \ (*p2) = (u32)(__val >> 32); \ __err; \ Loading @@ -158,7 +158,7 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) #define rdpmc(counter, low, high) \ do { \ u64 _l = native_read_pmc(counter); \ u64 _l = native_read_pmc((counter)); \ (low) = (u32)_l; \ (high) = (u32)(_l >> 32); \ } while (0) Loading @@ -175,16 +175,18 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) #endif /* !CONFIG_PARAVIRT */ #define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32)) #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ (u32)((val) >> 32)) #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2)) #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0) #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0) #ifdef CONFIG_SMP void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); #else /* CONFIG_SMP */ static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) Loading @@ -195,7 +197,8 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) { wrmsr(msr_no, l, h); } static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) { return rdmsr_safe(msr_no, l, h); } Loading