Commit abf0a19c authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Dmitry Baryshkov
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dt-bindings: display/msm: merge SM8450 DPU into SC7280 



Split of the bindings was artificial and not helping - we end up with
multiple binding files for very similar devices thus increasing the
chances of using different order of reg and clocks entries.

Unify DPU bindings of SC7280 and SM8450, because they are the same.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/617873/
Link: https://lore.kernel.org/r/20241003-dt-binding-display-msm-merge-v1-4-91ab08fc76a2@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 30c38fcd

Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: Qualcomm Display DPU on SC7280 


maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

  - Krishna Manikandan <quic_mkrishn@quicinc.com>



$ref: /schemas/display/msm/dpu-common.yaml#
@@ -18,6 +19,7 @@ properties: 
      - qcom,sc7280-dpu

      - qcom,sc8280xp-dpu

      - qcom,sm8350-dpu

      - qcom,sm8450-dpu



  reg:

    items:

Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml

deleted100644 → 0
+0 −139
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SM8450 Display DPU



maintainers:

  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>



$ref: /schemas/display/msm/dpu-common.yaml#



properties:

  compatible:

    const: qcom,sm8450-dpu



  reg:

    items:

      - description: Address offset and size for mdp register set

      - description: Address offset and size for vbif register set



  reg-names:

    items:

      - const: mdp

      - const: vbif



  clocks:

    items:

      - description: Display hf axi

      - description: Display sf axi

      - description: Display ahb

      - description: Display lut

      - description: Display core

      - description: Display vsync



  clock-names:

    items:

      - const: bus

      - const: nrt_bus

      - const: iface

      - const: lut

      - const: core

      - const: vsync



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm8450-dispcc.h>

    #include <dt-bindings/clock/qcom,gcc-sm8450.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interconnect/qcom,sm8450.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    display-controller@ae01000 {

        compatible = "qcom,sm8450-dpu";

        reg = <0x0ae01000 0x8f000>,

              <0x0aeb0000 0x2008>;

        reg-names = "mdp", "vbif";



        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                <&gcc GCC_DISP_SF_AXI_CLK>,

                <&dispcc DISP_CC_MDSS_AHB_CLK>,

                <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

                <&dispcc DISP_CC_MDSS_MDP_CLK>,

                <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

        clock-names = "bus",

                      "nrt_bus",

                      "iface",

                      "lut",

                      "core",

                      "vsync";



        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

        assigned-clock-rates = <19200000>;



        operating-points-v2 = <&mdp_opp_table>;

        power-domains = <&rpmhpd RPMHPD_MMCX>;



        interrupt-parent = <&mdss>;

        interrupts = <0>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                dpu_intf1_out: endpoint {

                    remote-endpoint = <&dsi0_in>;

                };

            };



            port@1 {

                reg = <1>;

                dpu_intf2_out: endpoint {

                    remote-endpoint = <&dsi1_in>;

                };

            };

        };



        mdp_opp_table: opp-table {

            compatible = "operating-points-v2";



            opp-172000000{

                opp-hz = /bits/ 64 <172000000>;

                required-opps = <&rpmhpd_opp_low_svs_d1>;

            };



            opp-200000000 {

                opp-hz = /bits/ 64 <200000000>;

                required-opps = <&rpmhpd_opp_low_svs>;

            };



            opp-325000000 {

                opp-hz = /bits/ 64 <325000000>;

                required-opps = <&rpmhpd_opp_svs>;

            };



            opp-375000000 {

                opp-hz = /bits/ 64 <375000000>;

                required-opps = <&rpmhpd_opp_svs_l1>;

            };



            opp-500000000 {

                opp-hz = /bits/ 64 <500000000>;

                required-opps = <&rpmhpd_opp_nom>;

            };

        };

    };

...