Commit abf5bac6 authored by Dikshita Agarwal's avatar Dikshita Agarwal Committed by Hans Verkuil
Browse files

media: iris: implement the boot sequence of the firmware 



Set the memory region on the firmware and implement the boot sequence.

Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org> # x1e80100 (Dell XPS 13 9345)
Reviewed-by: default avatarStefan Schmidt <stefan.schmidt@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Signed-off-by: default avatarDikshita Agarwal <quic_dikshita@quicinc.com>
Signed-off-by: default avatarHans Verkuil <hverkuil@xs4all.nl>
parent d19b1633

drivers/media/platform/qcom/iris/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -6,5 +6,6 @@ iris-objs += iris_core.o \ 
             iris_platform_sm8550.o \

             iris_probe.o \

             iris_vidc.o \

             iris_vpu_common.o \



obj-$(CONFIG_VIDEO_QCOM_IRIS) += iris.o

drivers/media/platform/qcom/iris/iris_core.c

+7 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include "iris_core.h"

#include "iris_firmware.h"

#include "iris_state.h"

#include "iris_vpu_common.h"



void iris_core_deinit(struct iris_core *core)

{
@@ -39,10 +40,16 @@ int iris_core_init(struct iris_core *core) 
	if (ret)

		goto error_queue_deinit;



	ret = iris_vpu_boot_firmware(core);

	if (ret)

		goto error_unload_fw;



	mutex_unlock(&core->lock);



	return 0;



error_unload_fw:

	iris_fw_unload(core);

error_queue_deinit:

	iris_hfi_queues_deinit(core);

error:

drivers/media/platform/qcom/iris/iris_platform_common.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ struct iris_platform_data { 
	const char *fwname;

	u32 pas_id;

	struct tz_cp_config *tz_cp_config_data;

	u32 core_arch;

};



#endif

drivers/media/platform/qcom/iris/iris_platform_sm8550.c

+3 −0
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 
#include "iris_hfi_gen2.h"

#include "iris_platform_common.h"



#define VIDEO_ARCH_LX 1



static const struct icc_info sm8550_icc_table[] = {

	{ "cpu-cfg",    1000, 1000     },

	{ "video-mem",  1000, 15000000 },
@@ -48,4 +50,5 @@ struct iris_platform_data sm8550_data = { 
	.fwname = "qcom/vpu/vpu30_p4.mbn",

	.pas_id = IRIS_PAS_ID,

	.tz_cp_config_data = &tz_cp_config_sm8550,

	.core_arch = VIDEO_ARCH_LX,

};

drivers/media/platform/qcom/iris/iris_vpu_common.c

0 → 100644
+89 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/iopoll.h>



#include "iris_core.h"

#include "iris_vpu_common.h"



#define CPU_BASE_OFFS				0x000A0000



#define CPU_CS_BASE_OFFS			(CPU_BASE_OFFS)



#define CTRL_INIT				(CPU_CS_BASE_OFFS + 0x48)

#define CTRL_STATUS				(CPU_CS_BASE_OFFS + 0x4C)



#define CTRL_ERROR_STATUS__M			0xfe



#define QTBL_INFO				(CPU_CS_BASE_OFFS + 0x50)

#define QTBL_ENABLE				BIT(0)



#define QTBL_ADDR				(CPU_CS_BASE_OFFS + 0x54)

#define CPU_CS_SCIACMDARG3			(CPU_CS_BASE_OFFS + 0x58)

#define SFR_ADDR				(CPU_CS_BASE_OFFS + 0x5C)

#define UC_REGION_ADDR				(CPU_CS_BASE_OFFS + 0x64)

#define UC_REGION_SIZE				(CPU_CS_BASE_OFFS + 0x68)



#define CPU_CS_H2XSOFTINTEN			(CPU_CS_BASE_OFFS + 0x148)

#define HOST2XTENSA_INTR_ENABLE			BIT(0)



#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)



static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core)

{

	u32 queue_size, value;



	/* Iris hardware requires 4K queue alignment */

	queue_size = ALIGN(sizeof(struct iris_hfi_queue_table_header) +

		(IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K);



	value = (u32)core->iface_q_table_daddr;

	writel(value, core->reg_base + UC_REGION_ADDR);



	/* Iris hardware requires 1M queue alignment */

	value = ALIGN(SFR_SIZE + queue_size, SZ_1M);

	writel(value, core->reg_base + UC_REGION_SIZE);



	value = (u32)core->iface_q_table_daddr;

	writel(value, core->reg_base + QTBL_ADDR);



	writel(QTBL_ENABLE, core->reg_base + QTBL_INFO);



	if (core->sfr_daddr) {

		value = (u32)core->sfr_daddr + core->iris_platform_data->core_arch;

		writel(value, core->reg_base + SFR_ADDR);

	}

}



int iris_vpu_boot_firmware(struct iris_core *core)

{

	u32 ctrl_init = BIT(0), ctrl_status = 0, count = 0, max_tries = 1000;



	iris_vpu_setup_ucregion_memory_map(core);



	writel(ctrl_init, core->reg_base + CTRL_INIT);

	writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3);



	while (!ctrl_status && count < max_tries) {

		ctrl_status = readl(core->reg_base + CTRL_STATUS);

		if ((ctrl_status & CTRL_ERROR_STATUS__M) == 0x4) {

			dev_err(core->dev, "invalid setting for uc_region\n");

			break;

		}



		usleep_range(50, 100);

		count++;

	}



	if (count >= max_tries) {

		dev_err(core->dev, "error booting up iris firmware\n");

		return -ETIME;

	}



	writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN);

	writel(0x0, core->reg_base + CPU_CS_X2RPMH);



	return 0;

}