Unverified Commit abfbfb98 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'amlogic-arm64-dt-for-v6.18' of... 

Merge tag 'amlogic-arm64-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt

Amlogic ARM64 DT for v6.18:
- Add cache information to the Amlogic SoCs
- Add RTC node for Amlogic C3 SoC
- Fix PWM node for Amlogic C3 SoC
- Remove UHS capability for Odroid-C2 SDCard

* tag 'amlogic-arm64-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  arm64: dts: amlogic: gxbb-odroidc2: remove UHS capability for SD card
  dts: arm: amlogic: fix pwm node for c3
  arm64: dts: amlogic: sm1-bananapi: lower SD card speed for stability
  arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC
  arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS
  arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
  arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS
  arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC
  arm64: dts: amlogic: C3: Add RTC controller node

Link: https://lore.kernel.org/r/d40e7e96-4a7c-4e4f-b36f-750c6525b95c@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9f1bbcc4 663bfe77

arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi

+37 −0
Original line number Diff line number Diff line
@@ -17,6 +17,13 @@ cpu0: cpu@0 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x0>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		cpu1: cpu@1 {
@@ -24,6 +31,13 @@ cpu1: cpu@1 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x1>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		cpu2: cpu@2 {
@@ -31,6 +45,13 @@ cpu2: cpu@2 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x2>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		cpu3: cpu@3 {
@@ -38,6 +59,22 @@ cpu3: cpu@3 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x3>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x80000>; /* L2. 512 KB */

			cache-line-size = <64>;

			cache-sets = <512>;

		};

	};

arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi

+40 −1
Original line number Diff line number Diff line
@@ -23,6 +23,13 @@ cpu0: cpu@0 { 
			compatible = "arm,cortex-a35";

			reg = <0x0 0x0>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		cpu1: cpu@1 {
@@ -30,6 +37,22 @@ cpu1: cpu@1 { 
			compatible = "arm,cortex-a35";

			reg = <0x0 0x1>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x7d000>; /* L2. 512 KB */

			cache-line-size = <64>;

			cache-sets = <512>;

		};

	};
@@ -53,6 +76,13 @@ xtal: xtal-clk { 
		#clock-cells = <0>;

	};



	xtal_32k: xtal-clk-32k {

		compatible = "fixed-clock";

		clock-frequency = <32768>;

		clock-output-names = "xtal_32k";

		#clock-cells = <0>;

	};



	sm: secure-monitor {

		compatible = "amlogic,meson-gxbb-sm";
@@ -792,7 +822,7 @@ spicc1: spi@52000 { 
			pwm_mn: pwm@54000 {

				compatible = "amlogic,c3-pwm",

					     "amlogic,meson-s4-pwm";

				reg = <0x0 54000 0x0 0x24>;

				reg = <0x0 0x54000 0x0 0x24>;

				clocks = <&clkc_periphs CLKID_PWM_M>,

					 <&clkc_periphs CLKID_PWM_N>;

				#pwm-cells = <3>;
@@ -967,6 +997,15 @@ nand: nand-controller@8d000 { 
				clock-names = "core", "device";

				status = "disabled";

			};



			rtc@9a000 {

				compatible = "amlogic,c3-rtc",

					     "amlogic,a5-rtc";

				reg = <0x0 0x9a000 0x0 0x38>;

				interrupts = <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>;

				clocks = <&xtal_32k>, <&clkc_periphs CLKID_SYS_RTC>;

				clock-names = "osc", "sys";

			};

		};



		ethmac: ethernet@fdc00000 {

arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -18,6 +18,13 @@ cpu0: cpu@0 { 
			compatible = "arm,cortex-a55";

			reg = <0x0 0x0>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		cpu1: cpu@100 {
@@ -25,6 +32,13 @@ cpu1: cpu@100 { 
			compatible = "arm,cortex-a55";

			reg = <0x0 0x100>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		cpu2: cpu@200 {
@@ -32,6 +46,13 @@ cpu2: cpu@200 { 
			compatible = "arm,cortex-a55";

			reg = <0x0 0x200>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		cpu3: cpu@300 {
@@ -39,8 +60,23 @@ cpu3: cpu@300 { 
			compatible = "arm,cortex-a55";

			reg = <0x0 0x300>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

		};



		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x40000>; /* L2. 256 KB */

			cache-line-size = <64>;

			cache-sets = <512>;

		};



	};



	timer {

arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi

+74 −0
Original line number Diff line number Diff line
@@ -53,6 +53,13 @@ cpu100: cpu@100 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x100>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2_cache_l>;

		};



		cpu101: cpu@101 {
@@ -60,6 +67,13 @@ cpu101: cpu@101 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x101>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2_cache_l>;

		};



		cpu102: cpu@102 {
@@ -67,6 +81,13 @@ cpu102: cpu@102 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x102>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2_cache_l>;

		};



		cpu103: cpu@103 {
@@ -74,6 +95,13 @@ cpu103: cpu@103 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x103>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2_cache_l>;

		};



		cpu0: cpu@0 {
@@ -81,6 +109,13 @@ cpu0: cpu@0 { 
			compatible = "arm,cortex-a73";

			reg = <0x0 0x0>;

			enable-method = "psci";

			d-cache-line-size = <64>;

			d-cache-size = <0x10000>;

			d-cache-sets = <64>;

			i-cache-line-size = <64>;

			i-cache-size = <0x10000>;

			i-cache-sets = <64>;

			next-level-cache = <&l2_cache_b>;

		};



		cpu1: cpu@1 {
@@ -88,6 +123,13 @@ cpu1: cpu@1 { 
			compatible = "arm,cortex-a73";

			reg = <0x0 0x1>;

			enable-method = "psci";

			d-cache-line-size = <64>;

			d-cache-size = <0x10000>;

			d-cache-sets = <64>;

			i-cache-line-size = <64>;

			i-cache-size = <0x10000>;

			i-cache-sets = <64>;

			next-level-cache = <&l2_cache_b>;

		};



		cpu2: cpu@2 {
@@ -95,6 +137,13 @@ cpu2: cpu@2 { 
			compatible = "arm,cortex-a73";

			reg = <0x0 0x2>;

			enable-method = "psci";

			d-cache-line-size = <64>;

			d-cache-size = <0x10000>;

			d-cache-sets = <64>;

			i-cache-line-size = <64>;

			i-cache-size = <0x10000>;

			i-cache-sets = <64>;

			next-level-cache = <&l2_cache_b>;

		};



		cpu3: cpu@3 {
@@ -102,6 +151,31 @@ cpu3: cpu@3 { 
			compatible = "arm,cortex-a73";

			reg = <0x0 0x3>;

			enable-method = "psci";

			d-cache-line-size = <64>;

			d-cache-size = <0x10000>;

			d-cache-sets = <64>;

			i-cache-line-size = <64>;

			i-cache-size = <0x10000>;

			i-cache-sets = <64>;

			next-level-cache = <&l2_cache_b>;

		};



		l2_cache_l: l2-cache-cluster0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x40000>;  /* L2. 256 KB */

			cache-line-size = <64>;

			cache-sets = <512>;

		};



		l2_cache_b: l2-cache-cluster1 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x100000>; /* L2. 1 Mb */

			cache-line-size = <64>;

			cache-sets = <512>;

		};

	};

arch/arm64/boot/dts/amlogic/meson-a1.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -27,6 +27,12 @@ cpu0: cpu@0 { 
			compatible = "arm,cortex-a35";

			reg = <0x0 0x0>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};
@@ -36,6 +42,12 @@ cpu1: cpu@1 { 
			compatible = "arm,cortex-a35";

			reg = <0x0 0x1>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};
@@ -44,6 +56,9 @@ l2: l2-cache0 { 
			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x80000>; /* L2. 512 KB */

			cache-line-size = <64>;

			cache-sets = <512>;

		};

	};