Commit ac160871 authored by Shuai Xue's avatar Shuai Xue Committed by Will Deacon
Browse files

PCI: Move pci_clear_and_set_dword() helper to PCI header 



The clear and set pattern is commonly used for accessing PCI config,
move the helper pci_clear_and_set_dword() from aspm.c into PCI header.
In addition, rename to pci_clear_and_set_config_dword() to retain the
"config" information and match the other accessors.

No functional change intended.

Signed-off-by: default avatarShuai Xue <xueshuai@linux.alibaba.com>
Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Tested-by: default avatarIlkka Koskinen <ilkka@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20231208025652.87192-4-xueshuai@linux.alibaba.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent ad6534c6

drivers/pci/access.c

+12 −0
Original line number Diff line number Diff line
@@ -598,3 +598,15 @@ int pci_write_config_dword(const struct pci_dev *dev, int where, 
	return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);

}

EXPORT_SYMBOL(pci_write_config_dword);



void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,

				    u32 clear, u32 set)

{

	u32 val;



	pci_read_config_dword(dev, pos, &val);

	val &= ~clear;

	val |= set;

	pci_write_config_dword(dev, pos, val);

}

EXPORT_SYMBOL(pci_clear_and_set_config_dword);

drivers/pci/pcie/aspm.c

+30 −35
Original line number Diff line number Diff line
@@ -426,17 +426,6 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) 
	}

}



static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,

				    u32 clear, u32 set)

{

	u32 val;



	pci_read_config_dword(pdev, pos, &val);

	val &= ~clear;

	val |= set;

	pci_write_config_dword(pdev, pos, val);

}



/* Calculate L1.2 PM substate timing parameters */

static void aspm_calc_l12_info(struct pcie_link_state *link,

				u32 parent_l1ss_cap, u32 child_l1ss_cap)
@@ -501,9 +490,11 @@ static void aspm_calc_l12_info(struct pcie_link_state *link, 
	cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;



	if (pl1_2_enables || cl1_2_enables) {

		pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,

		pci_clear_and_set_config_dword(child,

					       child->l1ss + PCI_L1SS_CTL1,

					       PCI_L1SS_CTL1_L1_2_MASK, 0);

		pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

		pci_clear_and_set_config_dword(parent,

					       parent->l1ss + PCI_L1SS_CTL1,

					       PCI_L1SS_CTL1_L1_2_MASK, 0);

	}
@@ -512,21 +503,25 @@ static void aspm_calc_l12_info(struct pcie_link_state *link, 
	pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);



	/* Program Common_Mode_Restore_Time in upstream device */

	pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

	pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

				       PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);



	/* Program LTR_L1.2_THRESHOLD time in both ports */

	pci_clear_and_set_dword(parent,	parent->l1ss + PCI_L1SS_CTL1,

	pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

				       PCI_L1SS_CTL1_LTR_L12_TH_VALUE |

				PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);

	pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,

				       PCI_L1SS_CTL1_LTR_L12_TH_SCALE,

				       ctl1);

	pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,

				       PCI_L1SS_CTL1_LTR_L12_TH_VALUE |

				PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);

				       PCI_L1SS_CTL1_LTR_L12_TH_SCALE,

				       ctl1);



	if (pl1_2_enables || cl1_2_enables) {

		pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,

		pci_clear_and_set_config_dword(parent,

					       parent->l1ss + PCI_L1SS_CTL1, 0,

					       pl1_2_enables);

		pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,

		pci_clear_and_set_config_dword(child,

					       child->l1ss + PCI_L1SS_CTL1, 0,

					       cl1_2_enables);

	}

}
@@ -687,9 +682,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) 
	 */



	/* Disable all L1 substates */

	pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,

	pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,

				       PCI_L1SS_CTL1_L1SS_MASK, 0);

	pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

	pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

				       PCI_L1SS_CTL1_L1SS_MASK, 0);

	/*

	 * If needed, disable L1, and it gets enabled later
@@ -713,9 +708,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) 
		val |= PCI_L1SS_CTL1_PCIPM_L1_2;



	/* Enable what we need to enable */

	pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

	pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

				       PCI_L1SS_CTL1_L1SS_MASK, val);

	pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,

	pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,

				       PCI_L1SS_CTL1_L1SS_MASK, val);

}

include/linux/pci.h

+2 −0
Original line number Diff line number Diff line
@@ -1239,6 +1239,8 @@ int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 
int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);

int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);

int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);

void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,

				    u32 clear, u32 set);



int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);

int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);