Commit ac89d11b authored by Artem Bityutskiy's avatar Artem Bityutskiy Committed by Rafael J. Wysocki
Browse files

intel_idle: add Grand Ridge SoC support 



Add Intel Grand Ridge SoC C-states, which are C1, C1E, and C6S.

The Grand Ridge SoC is built with modules, each module includes 4 cores
(Crestmont microarchitecture). There is one L2 cache per module, shared
between the 4 cores.

There is no core C6 state, but there is C6S state, which has module
scope: when all 4 cores request C6S, the entire module (4 cores + L2
cache) enters the low power state.

Package C6 is not supported by Grand Ridge SoC.

Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent eeae55ed

drivers/idle/intel_idle.c

+36 −0
Original line number Diff line number Diff line
@@ -1271,6 +1271,35 @@ static struct cpuidle_state snr_cstates[] __initdata = { 
		.enter = NULL }

};



static struct cpuidle_state grr_cstates[] __initdata = {

	{

		.name = "C1",

		.desc = "MWAIT 0x00",

		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE,

		.exit_latency = 1,

		.target_residency = 1,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C1E",

		.desc = "MWAIT 0x01",

		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,

		.exit_latency = 2,

		.target_residency = 10,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C6S",

		.desc = "MWAIT 0x22",

		.flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 140,

		.target_residency = 500,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.enter = NULL }

};



static const struct idle_cpu idle_cpu_nehalem __initconst = {

	.state_table = nehalem_cstates,

	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
@@ -1420,6 +1449,12 @@ static const struct idle_cpu idle_cpu_snr __initconst = { 
	.use_acpi = true,

};



static const struct idle_cpu idle_cpu_grr __initconst = {

	.state_table = grr_cstates,

	.disable_promotion_to_c1e = true,

	.use_acpi = true,

};



static const struct x86_cpu_id intel_idle_ids[] __initconst = {

	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP,		&idle_cpu_nhx),

	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM,		&idle_cpu_nehalem),
@@ -1466,6 +1501,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS,	&idle_cpu_bxt),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,	&idle_cpu_dnv),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&idle_cpu_snr),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT,	&idle_cpu_grr),

	{}

};