Commit acae8ad6 authored by Asad Kamal's avatar Asad Kamal Committed by Alex Deucher
Browse files

drm/amd/pm: Fetch npm data from system metrics table



Fetch npm data from system metrics table for smu_v13_0_12

v3: Remove intermittent type for npm data, remove node id check,
move npm caps check to npm_get_data function (Lijo)

Signed-off-by: default avatarAsad Kamal <asad.kamal@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarYang Wang <kevinyang.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ef612f58
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+47 −0
Original line number Diff line number Diff line
@@ -341,6 +341,9 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu)
			static_metrics->pldmVersion[0] != 0xFFFFFFFF)
			smu->adev->firmware.pldm_version =
				static_metrics->pldmVersion[0];
		if (smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS)))
			pptable->MaxNodePowerLimit =
				SMUQ10_ROUND(static_metrics->MaxNodePowerLimit);
		smu_v13_0_12_init_xgmi_data(smu, static_metrics);
		pptable->Init = true;
	}
@@ -580,6 +583,50 @@ static bool smu_v13_0_12_is_temp_metrics_supported(struct smu_context *smu,
	return false;
}

int smu_v13_0_12_get_npm_data(struct smu_context *smu,
			      enum amd_pp_sensors sensor,
			      uint32_t *value)
{
	struct smu_table_context *smu_table = &smu->smu_table;
	struct PPTable_t *pptable =
		(struct PPTable_t *)smu_table->driver_pptable;
	struct smu_table *tables = smu_table->tables;
	SystemMetricsTable_t *metrics;
	struct smu_table *sys_table;
	int ret;

	if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS)))
		return -EOPNOTSUPP;

	if (sensor == AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT) {
		*value = pptable->MaxNodePowerLimit;
		return 0;
	}

	ret = smu_v13_0_12_get_system_metrics_table(smu);
	if (ret)
		return ret;

	sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS];
	metrics = (SystemMetricsTable_t *)sys_table->cache.buffer;

	switch (sensor) {
	case AMDGPU_PP_SENSOR_NODEPOWERLIMIT:
		*value = SMUQ10_ROUND(metrics->NodePowerLimit);
		break;
	case AMDGPU_PP_SENSOR_NODEPOWER:
		*value = SMUQ10_ROUND(metrics->NodePower);
		break;
	case AMDGPU_PP_SENSOR_GPPTRESIDENCY:
		*value = SMUQ10_ROUND(metrics->GlobalPPTResidencyAcc);
		break;
	default:
		return -EINVAL;
	}

	return ret;
}

static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu,
					     enum smu_temp_metric_type type, void *table)
{
+9 −0
Original line number Diff line number Diff line
@@ -1801,6 +1801,15 @@ static int smu_v13_0_6_read_sensor(struct smu_context *smu,
			ret = -EOPNOTSUPP;
			break;
		}
	case AMDGPU_PP_SENSOR_NODEPOWERLIMIT:
	case AMDGPU_PP_SENSOR_NODEPOWER:
	case AMDGPU_PP_SENSOR_GPPTRESIDENCY:
	case AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT:
		ret = smu_v13_0_12_get_npm_data(smu, sensor, (uint32_t *)data);
		if (ret)
			return ret;
		*size = 4;
		break;
	case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
	default:
		ret = -EOPNOTSUPP;
+5 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ struct PPTable_t {
	uint32_t MaxLclkDpmRange;
	uint32_t MinLclkDpmRange;
	uint64_t PublicSerialNumber_AID;
	uint32_t MaxNodePowerLimit;
	bool Init;
};

@@ -70,6 +71,7 @@ enum smu_v13_0_6_caps {
	SMU_CAP(BOARD_VOLTAGE),
	SMU_CAP(PLDM_VERSION),
	SMU_CAP(TEMP_METRICS),
	SMU_CAP(NPM_METRICS),
	SMU_CAP(ALL),
};

@@ -91,6 +93,9 @@ ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu,
				     void *smu_metrics);
int smu_v13_0_12_tables_init(struct smu_context *smu);
void smu_v13_0_12_tables_fini(struct smu_context *smu);
int smu_v13_0_12_get_npm_data(struct smu_context *smu,
			      enum amd_pp_sensors sensor,
			      uint32_t *value);
extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[];
extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[];
extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs;