Commit acb727e0 authored by Dapeng Mi's avatar Dapeng Mi Committed by Ingo Molnar
Browse files

perf/x86/intel: Rename x86_pmu.pebs to x86_pmu.ds_pebs 



Since architectural PEBS would be introduced in subsequent patches,
rename x86_pmu.pebs to x86_pmu.ds_pebs for distinguishing with the
upcoming architectural PEBS.

Besides restrict reserve_ds_buffers() helper to work only for the
legacy DS based PEBS and avoid it to corrupt the pebs_active flag and
release PEBS buffer incorrectly for arch-PEBS since the later patch
would reuse these flags and alloc/release_pebs_buffer() helpers for
arch-PEBS.

Signed-off-by: default avatarDapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Link: https://lkml.kernel.org/r/20250415114428.341182-6-dapeng1.mi@linux.intel.com
parent d971342d

arch/x86/events/intel/core.c

+3 −3
Original line number Diff line number Diff line
@@ -4584,7 +4584,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 
		.guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,

	};



	if (!x86_pmu.pebs)

	if (!x86_pmu.ds_pebs)

		return arr;



	/*
@@ -5764,7 +5764,7 @@ static __init void intel_clovertown_quirk(void) 
	 * these chips.

	 */

	pr_warn("PEBS disabled due to CPU errata\n");

	x86_pmu.pebs = 0;

	x86_pmu.ds_pebs = 0;

	x86_pmu.pebs_constraints = NULL;

}
@@ -6252,7 +6252,7 @@ tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 
static umode_t

pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)

{

	return x86_pmu.pebs ? attr->mode : 0;

	return x86_pmu.ds_pebs ? attr->mode : 0;

}



static umode_t

arch/x86/events/intel/ds.c

+18 −14
Original line number Diff line number Diff line
@@ -624,7 +624,7 @@ static int alloc_pebs_buffer(int cpu) 
	int max, node = cpu_to_node(cpu);

	void *buffer, *insn_buff, *cea;



	if (!x86_pmu.pebs)

	if (!x86_pmu.ds_pebs)

		return 0;



	buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
@@ -659,7 +659,7 @@ static void release_pebs_buffer(int cpu) 
	struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);

	void *cea;



	if (!x86_pmu.pebs)

	if (!x86_pmu.ds_pebs)

		return;



	kfree(per_cpu(insn_buffer, cpu));
@@ -734,7 +734,7 @@ void release_ds_buffers(void) 
{

	int cpu;



	if (!x86_pmu.bts && !x86_pmu.pebs)

	if (!x86_pmu.bts && !x86_pmu.ds_pebs)

		return;



	for_each_possible_cpu(cpu)
@@ -750,6 +750,7 @@ void release_ds_buffers(void) 
	}



	for_each_possible_cpu(cpu) {

		if (x86_pmu.ds_pebs)

			release_pebs_buffer(cpu);

		release_bts_buffer(cpu);

	}
@@ -761,15 +762,17 @@ void reserve_ds_buffers(void) 
	int cpu;



	x86_pmu.bts_active = 0;



	if (x86_pmu.ds_pebs)

		x86_pmu.pebs_active = 0;



	if (!x86_pmu.bts && !x86_pmu.pebs)

	if (!x86_pmu.bts && !x86_pmu.ds_pebs)

		return;



	if (!x86_pmu.bts)

		bts_err = 1;



	if (!x86_pmu.pebs)

	if (!x86_pmu.ds_pebs)

		pebs_err = 1;



	for_each_possible_cpu(cpu) {
@@ -781,7 +784,8 @@ void reserve_ds_buffers(void) 
		if (!bts_err && alloc_bts_buffer(cpu))

			bts_err = 1;



		if (!pebs_err && alloc_pebs_buffer(cpu))

		if (x86_pmu.ds_pebs && !pebs_err &&

		    alloc_pebs_buffer(cpu))

			pebs_err = 1;



		if (bts_err && pebs_err)
@@ -793,7 +797,7 @@ void reserve_ds_buffers(void) 
			release_bts_buffer(cpu);

	}



	if (pebs_err) {

	if (x86_pmu.ds_pebs && pebs_err) {

		for_each_possible_cpu(cpu)

			release_pebs_buffer(cpu);

	}
@@ -805,7 +809,7 @@ void reserve_ds_buffers(void) 
		if (x86_pmu.bts && !bts_err)

			x86_pmu.bts_active = 1;



		if (x86_pmu.pebs && !pebs_err)

		if (x86_pmu.ds_pebs && !pebs_err)

			x86_pmu.pebs_active = 1;



		for_each_possible_cpu(cpu) {
@@ -2662,12 +2666,12 @@ void __init intel_pebs_init(void) 
	if (!boot_cpu_has(X86_FEATURE_DTES64))

		return;



	x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);

	x86_pmu.ds_pebs = boot_cpu_has(X86_FEATURE_PEBS);

	x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;

	if (x86_pmu.version <= 4)

		x86_pmu.pebs_no_isolation = 1;



	if (x86_pmu.pebs) {

	if (x86_pmu.ds_pebs) {

		char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';

		char *pebs_qual = "";

		int format = x86_pmu.intel_cap.pebs_format;
@@ -2759,7 +2763,7 @@ void __init intel_pebs_init(void) 


		default:

			pr_cont("no PEBS fmt%d%c, ", format, pebs_type);

			x86_pmu.pebs = 0;

			x86_pmu.ds_pebs = 0;

		}

	}

}
@@ -2768,7 +2772,7 @@ void perf_restore_debug_store(void) 
{

	struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);



	if (!x86_pmu.bts && !x86_pmu.pebs)

	if (!x86_pmu.bts && !x86_pmu.ds_pebs)

		return;



	wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);

arch/x86/events/perf_event.h

+1 −1
Original line number Diff line number Diff line
@@ -898,7 +898,7 @@ struct x86_pmu { 
	 */

	unsigned int	bts			:1,

			bts_active		:1,

			pebs			:1,

			ds_pebs			:1,

			pebs_active		:1,

			pebs_broken		:1,

			pebs_prec_dist		:1,