Commit acdc43f2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/mes: update hqd masks when disable_kq is set 



Make all resources available to user queues.

Reviewed-by: default avatarPrike Liang <Prike.Liang@amd.com>
Suggested-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Reviewed-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f091fa77

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+3 −3
Original line number Diff line number Diff line
@@ -124,14 +124,14 @@ int amdgpu_mes_init(struct amdgpu_device *adev) 
			 * Set GFX pipe 0 queue 1-7 for MES scheduling

			 * mask = 1111 1110b

			 */

			adev->mes.gfx_hqd_mask[i] = 0xFE;

			adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0xFF : 0xFE;

		else

			/*

			 * GFX pipe 0 queue 0 is being used by Kernel queue.

			 * Set GFX pipe 0 queue 1 for MES scheduling

			 * mask = 10b

			 */

			adev->mes.gfx_hqd_mask[i] = 0x2;

			adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 : 0x2;

	}



	num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec;
@@ -142,7 +142,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev) 
	for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {

		if (i >= num_pipes)

			break;

		adev->mes.compute_hqd_mask[i] = 0xc;

		adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF : 0xC;

	}



	num_pipes = adev->sdma.num_instances;