Commit ad227dab authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks 



Add definitions for USB2 PHY core clocks and Gigabit Ethernet PTP
reference core clocks in the R9A09G057 CPG DT bindings header file.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-8-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 3e4863d2

include/dt-bindings/clock/renesas,r9a09g057-cpg.h

+4 −0
Original line number Diff line number Diff line
@@ -17,5 +17,9 @@ 
#define R9A09G057_CM33_CLK0			6

#define R9A09G057_CST_0_SWCLKTCK		7

#define R9A09G057_IOTOP_0_SHCLK			8

#define R9A09G057_USB2_0_CLK_CORE0		9

#define R9A09G057_USB2_0_CLK_CORE1		10

#define R9A09G057_GBETH_0_CLK_PTP_REF_I		11

#define R9A09G057_GBETH_1_CLK_PTP_REF_I		12



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */