Commit ad97e72f authored by Hariprasad Kelam's avatar Hariprasad Kelam Committed by Jakub Kicinski
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Octeontx2-af: Introduce mode group index 



Kernel and firmware communicates via scratch register which is
64 bit in size.

[MODE_ID   PORT    AUTONEG  DUPLEX  SPEED   CMD_ID   OWNERSHIP ]
 63-22     21-14     13      12      11-8    7-2       1-0

The existing MODE_ID bitmap can only support up to 42 modes.
To resolve the issue, the unused port field is modified as below
            uint64_t reserved2:6;
            uint64_t mode_group_idx:2;

'mode_group_idx' categorize the mode ID range to accommodate more modes.

	To specify mode ID range of 0 - 41, this field will be 0.

    	To specify mode ID range of 42 - 83, this field will be 1.

mode ID will be still mentioned as 1 << (0 - 41).  But the mode_group_idx
decides the actual mode range

Signed-off-by: default avatarHariprasad Kelam <hkelam@marvell.com>
Link: https://patch.msgid.link/20250625092107.9746-3-hkelam@marvell.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 1df77da0

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+15 −2
Original line number Diff line number Diff line
@@ -1182,6 +1182,9 @@ static int cgx_link_usertable_index_map(int speed) 
static void set_mod_args(struct cgx_set_link_mode_args *args,

			 u32 speed, u8 duplex, u8 autoneg, u64 mode)

{

	int mode_baseidx;

	u8 cgx_mode;



	/* Fill default values incase of user did not pass

	 * valid parameters

	 */
@@ -1191,8 +1194,18 @@ static void set_mod_args(struct cgx_set_link_mode_args *args, 
		args->speed = speed;

	if (args->an == AUTONEG_UNKNOWN)

		args->an = autoneg;



	/* Derive mode_base_idx and mode fields based

	 * on cgx_mode value

	 */

	cgx_mode = find_first_bit((unsigned long *)&mode,

				  CGX_MODE_MAX);

	args->mode = mode;

	args->ports = 0;

	mode_baseidx = cgx_mode - 41;

	if (mode_baseidx > 0) {

		args->mode_baseidx = 1;

		args->mode = BIT_ULL(mode_baseidx);

	}

}



static void otx2_map_ethtool_link_modes(u64 bitmask,
@@ -1499,7 +1512,7 @@ int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, 
			cgx_link_usertable_index_map(args.speed), req);

	req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req);

	req = FIELD_SET(CMDMODECHANGE_AN, args.an, req);

	req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req);

	req = FIELD_SET(CMDMODECHANGE_MODE_BASEIDX, args.mode_baseidx, req);

	req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req);



	return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

+6 −1
Original line number Diff line number Diff line
@@ -282,7 +282,12 @@ struct cgx_lnk_sts { 
#define CMDMODECHANGE_SPEED		GENMASK_ULL(11, 8)

#define CMDMODECHANGE_DUPLEX		GENMASK_ULL(12, 12)

#define CMDMODECHANGE_AN		GENMASK_ULL(13, 13)

#define CMDMODECHANGE_PORT		GENMASK_ULL(21, 14)

/* this field categorize the mode ID(FLAGS) range to accommodate

 * more modes.

 * To specify mode ID range of 0 - 41, this field will be 0.

 * To specify mode ID range of 42 - 83, this field will be 1.

 */

#define CMDMODECHANGE_MODE_BASEIDX	GENMASK_ULL(21, 20)

#define CMDMODECHANGE_FLAGS		GENMASK_ULL(63, 22)



/* LINK_BRING_UP command timeout */

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+1 −1
Original line number Diff line number Diff line
@@ -675,7 +675,7 @@ struct cgx_set_link_mode_args { 
	u32 speed;

	u8 duplex;

	u8 an;

	u8 ports;

	u8 mode_baseidx;

	u64 mode;

};