Commit adf346e5 authored by Youling Tang's avatar Youling Tang Committed by Huacai Chen
Browse files

LoongArch: Add flush_icache_all()/local_flush_icache_all() 



LoongArch maintains ICache/DCache coherency by hardware, so we just need
"ibar 0" to avoid instruction hazard here.

Signed-off-by: default avatarYouling Tang <tangyouling@kylinos.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 0c965d27

arch/loongarch/include/asm/cacheflush.h

+15 −1
Original line number Diff line number Diff line
@@ -32,8 +32,22 @@ static inline unsigned int cpu_last_level_cache_line_size(void) 
}



asmlinkage void __flush_cache_all(void);

void local_flush_icache_range(unsigned long start, unsigned long end);



/*

 * LoongArch maintains ICache/DCache coherency by hardware,

 * we just need "ibar" to avoid instruction hazard here.

 */

static inline void local_flush_icache_all(void)

{

	asm volatile ("ibar\t0\n"::);

}



static inline void local_flush_icache_range(unsigned long start, unsigned long end)

{

	asm volatile ("ibar\t0\n"::);

}



#define flush_icache_all	local_flush_icache_all

#define flush_icache_range	local_flush_icache_range

#define flush_icache_user_range	local_flush_icache_range

arch/loongarch/mm/cache.c

+0 −10
Original line number Diff line number Diff line
@@ -31,16 +31,6 @@ void cache_error_setup(void) 
	set_merr_handler(0x0, &except_vec_cex, 0x80);

}



/*

 * LoongArch maintains ICache/DCache coherency by hardware,

 * we just need "ibar" to avoid instruction hazard here.

 */

void local_flush_icache_range(unsigned long start, unsigned long end)

{

	asm volatile ("\tibar 0\n"::);

}

EXPORT_SYMBOL(local_flush_icache_range);



static void flush_cache_leaf(unsigned int leaf)

{

	int i, j, nr_nodes;