Unverified Commit ae62e7cf authored by Miquel Raynal (Schneider Electric)'s avatar Miquel Raynal (Schneider Electric) Committed by Mark Brown
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spi: cadence-qspi: Add a flag for controllers without indirect access support 



Renesas RZ/N1 QSPI controllers embed the Cadence IP with some
limitations/simplifications. One of the is that only direct access is
supported, none of the registers related to indirect writes are
populated, so create a flag to avoid these accesses and make sure only
direct accessors are called.

Tested-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: default avatarMiquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Tested-by: default avatarSanthosh Kumar K <s-k6@ti.com>
Link: https://patch.msgid.link/20260122-schneider-6-19-rc1-qspi-v4-11-f9c21419a3e6@bootlin.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 612227b3

drivers/spi/spi-cadence-quadspi.c

+16 −13
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX); 
#define CQSPI_SUPPORT_DEVICE_RESET	BIT(8)

#define CQSPI_DISABLE_STIG_MODE		BIT(9)

#define CQSPI_DISABLE_RUNTIME_PM	BIT(10)

#define CQSPI_NO_INDIRECT_MODE		BIT(11)



/* Capabilities */

#define CQSPI_SUPPORTS_OCTAL		BIT(0)
@@ -1425,7 +1426,8 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 
	if (ret)

		return ret;



	if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))

	if ((cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) ||

	    (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE))

		return cqspi_direct_read_execute(f_pdata, buf, from, len);



	if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
@@ -1626,9 +1628,9 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) 
	/* Disable all interrupts. */

	writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);



	if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) {

		/* Configure the SRAM split to 1:1 . */

		writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);



		/* Load indirect trigger address. */

		writel(cqspi->trigger_address,

		       cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
@@ -1639,6 +1641,7 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) 
		/* Program write watermark -- 1/8 of the FIFO. */

		writel(cqspi->fifo_depth * cqspi->fifo_width / 8,

		       cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);

	}



	/* Disable direct access controller */

	if (!cqspi->use_direct_mode) {