Commit ae67558b authored by Srinivasan Shanmugam's avatar Srinivasan Shanmugam Committed by Alex Deucher
Browse files

drm/amd/display: fix some coding style issues 



Fix the following checkpatch checks in amdgpu_dm.c

CHECK: Prefer kernel type 'u8' over 'uint8_t'
CHECK: Prefer kernel type 'u32' over 'uint32_t'
CHECK: Prefer kernel type 'u64' over 'uint64_t'
CHECK: Prefer kernel type 's32' over 'int32_t'

Signed-off-by: default avatarSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0b93c543

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+47 −47
Original line number Diff line number Diff line
@@ -210,7 +210,7 @@ static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 


static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,

				    struct amdgpu_dm_connector *amdgpu_dm_connector,

				    uint32_t link_index,

				    u32 link_index,

				    struct amdgpu_encoder *amdgpu_encoder);

static int amdgpu_dm_encoder_init(struct drm_device *dev,

				  struct amdgpu_encoder *aencoder,
@@ -262,7 +262,7 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 
static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,

				  u32 *vbl, u32 *position)

{

	uint32_t v_blank_start, v_blank_end, h_position, v_position;

	u32 v_blank_start, v_blank_end, h_position, v_position;



	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))

		return -EINVAL;
@@ -361,7 +361,7 @@ static void dm_pflip_high_irq(void *interrupt_params) 
	struct amdgpu_device *adev = irq_params->adev;

	unsigned long flags;

	struct drm_pending_vblank_event *e;

	uint32_t vpos, hpos, v_blank_start, v_blank_end;

	u32 vpos, hpos, v_blank_start, v_blank_end;

	bool vrr_active;



	amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
@@ -648,7 +648,7 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, 
	struct drm_connector *connector;

	struct drm_connector_list_iter iter;

	struct dc_link *link;

	uint8_t link_index = 0;

	u8 link_index = 0;

	struct drm_device *dev;



	if (adev == NULL)
@@ -749,7 +749,7 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params) 
	struct amdgpu_device *adev = irq_params->adev;

	struct amdgpu_display_manager *dm = &adev->dm;

	struct dmcub_trace_buf_entry entry = { 0 };

	uint32_t count = 0;

	u32 count = 0;

	struct dmub_hpd_work *dmub_hpd_wrk;

	struct dc_link *plink = NULL;
@@ -1015,7 +1015,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) 
	struct dmub_srv_hw_params hw_params;

	enum dmub_status status;

	const unsigned char *fw_inst_const, *fw_bss_data;

	uint32_t i, fw_inst_const_size, fw_bss_data_size;

	u32 i, fw_inst_const_size, fw_bss_data_size;

	bool has_hw_support;



	if (!dmub_srv)
@@ -1176,10 +1176,10 @@ static void dm_dmub_hw_resume(struct amdgpu_device *adev) 


static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)

{

	uint64_t pt_base;

	uint32_t logical_addr_low;

	uint32_t logical_addr_high;

	uint32_t agp_base, agp_bot, agp_top;

	u64 pt_base;

	u32 logical_addr_low;

	u32 logical_addr_high;

	u32 agp_base, agp_bot, agp_top;

	PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;



	memset(pa_config, 0, sizeof(*pa_config));
@@ -2493,7 +2493,7 @@ struct amdgpu_dm_connector * 
amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,

					     struct drm_crtc *crtc)

{

	uint32_t i;

	u32 i;

	struct drm_connector_state *new_con_state;

	struct drm_connector *connector;

	struct drm_crtc *crtc_from_state;
@@ -3126,8 +3126,8 @@ static void handle_hpd_irq(void *param) 


static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)

{

	uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };

	uint8_t dret;

	u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };

	u8 dret;

	bool new_irq_handled = false;

	int dpcd_addr;

	int dpcd_bytes_to_read;
@@ -3155,7 +3155,7 @@ static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) 


	while (dret == dpcd_bytes_to_read &&

		process_count < max_process_count) {

		uint8_t retry;

		u8 retry;

		dret = 0;



		process_count++;
@@ -3174,7 +3174,7 @@ static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) 
				dpcd_bytes_to_read - 1;



			for (retry = 0; retry < 3; retry++) {

				uint8_t wret;

				u8 wret;



				wret = drm_dp_dpcd_write(

					&aconnector->dm_dp_aux.aux,
@@ -4188,12 +4188,12 @@ static void amdgpu_set_panel_orientation(struct drm_connector *connector); 
static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)

{

	struct amdgpu_display_manager *dm = &adev->dm;

	int32_t i;

	s32 i;

	struct amdgpu_dm_connector *aconnector = NULL;

	struct amdgpu_encoder *aencoder = NULL;

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	uint32_t link_cnt;

	int32_t primary_planes;

	u32 link_cnt;

	s32 primary_planes;

	enum dc_connection_type new_connection_type = dc_connection_none;

	const struct dc_plane_cap *plane;

	bool psr_feature_enabled = false;
@@ -4706,7 +4706,7 @@ fill_plane_color_attributes(const struct drm_plane_state *plane_state, 
static int

fill_dc_plane_info_and_addr(struct amdgpu_device *adev,

			    const struct drm_plane_state *plane_state,

			    const uint64_t tiling_flags,

			    const u64 tiling_flags,

			    struct dc_plane_info *plane_info,

			    struct dc_plane_address *address,

			    bool tmz_surface,
@@ -4881,7 +4881,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, 


static inline void fill_dc_dirty_rect(struct drm_plane *plane,

				      struct rect *dirty_rect, int32_t x,

				      int32_t y, int32_t width, int32_t height,

				      s32 y, s32 width, s32 height,

				      int *i, bool ffu)

{

	if (*i > DC_MAX_DIRTY_RECTS)
@@ -4937,11 +4937,11 @@ static void fill_dc_dirty_rects(struct drm_plane *plane, 
{

	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);

	struct rect *dirty_rects = flip_addrs->dirty_rects;

	uint32_t num_clips;

	u32 num_clips;

	struct drm_mode_rect *clips;

	bool bb_changed;

	bool fb_changed;

	uint32_t i = 0;

	u32 i = 0;



	/*

	 * Cursor plane has it's own dirty rect update interface. See
@@ -5087,7 +5087,7 @@ static enum dc_color_depth 
convert_color_depth_from_display_info(const struct drm_connector *connector,

				      bool is_y420, int requested_bpc)

{

	uint8_t bpc;

	u8 bpc;



	if (is_y420) {

		bpc = 8;
@@ -5631,8 +5631,8 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 
				    uint32_t max_dsc_target_bpp_limit_override)

{

	const struct dc_link_settings *verified_link_cap = NULL;

	uint32_t link_bw_in_kbps;

	uint32_t edp_min_bpp_x16, edp_max_bpp_x16;

	u32 link_bw_in_kbps;

	u32 edp_min_bpp_x16, edp_max_bpp_x16;

	struct dc *dc = sink->ctx->dc;

	struct dc_dsc_bw_range bw_range = {0};

	struct dc_dsc_config dsc_cfg = {0};
@@ -5689,11 +5689,11 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 
					struct dsc_dec_dpcd_caps *dsc_caps)

{

	struct drm_connector *drm_connector = &aconnector->base;

	uint32_t link_bandwidth_kbps;

	u32 link_bandwidth_kbps;

	struct dc *dc = sink->ctx->dc;

	uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;

	uint32_t dsc_max_supported_bw_in_kbps;

	uint32_t max_dsc_target_bpp_limit_override =

	u32 max_supported_bw_in_kbps, timing_bw_in_kbps;

	u32 dsc_max_supported_bw_in_kbps;

	u32 max_dsc_target_bpp_limit_override =

		drm_connector->display_info.max_dsc_bpp;



	link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
@@ -6914,7 +6914,7 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 
	const struct drm_display_mode *m;

	struct drm_display_mode *new_mode;

	uint i;

	uint32_t new_modes_count = 0;

	u32 new_modes_count = 0;



	/* Standard FPS values

	 *
@@ -6928,7 +6928,7 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 
	 * 60 	        - Commonly used

	 * 48,72,96,120 - Multiples of 24

	 */

	static const uint32_t common_rates[] = {

	static const u32 common_rates[] = {

		23976, 24000, 25000, 29970, 30000,

		48000, 50000, 60000, 72000, 96000, 120000

	};
@@ -6944,8 +6944,8 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 
		return 0;



	for (i = 0; i < ARRAY_SIZE(common_rates); i++) {

		uint64_t target_vtotal, target_vtotal_diff;

		uint64_t num, den;

		u64 target_vtotal, target_vtotal_diff;

		u64 num, den;



		if (drm_mode_vrefresh(m) * 1000 < common_rates[i])

			continue;
@@ -7187,7 +7187,7 @@ create_i2c(struct ddc_service *ddc_service, 
 */

static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,

				    struct amdgpu_dm_connector *aconnector,

				    uint32_t link_index,

				    u32 link_index,

				    struct amdgpu_encoder *aencoder)

{

	int res = 0;
@@ -7671,8 +7671,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 
				    struct drm_crtc *pcrtc,

				    bool wait_for_vblank)

{

	uint32_t i;

	uint64_t timestamp_ns;

	u32 i;

	u64 timestamp_ns;

	struct drm_plane *plane;

	struct drm_plane_state *old_plane_state, *new_plane_state;

	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
@@ -7683,7 +7683,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 
			to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));

	int planes_count = 0, vpos, hpos;

	unsigned long flags;

	uint32_t target_vblank, last_flip_vblank;

	u32 target_vblank, last_flip_vblank;

	bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);

	bool cursor_update = false;

	bool pflip_present = false;
@@ -8121,7 +8121,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 
	struct amdgpu_display_manager *dm = &adev->dm;

	struct dm_atomic_state *dm_state;

	struct dc_state *dc_state = NULL, *dc_state_temp = NULL;

	uint32_t i, j;

	u32 i, j;

	struct drm_crtc *crtc;

	struct drm_crtc_state *old_crtc_state, *new_crtc_state;

	unsigned long flags;
@@ -8770,7 +8770,7 @@ is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 
}



static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {

	uint64_t num, den, res;

	u64 num, den, res;

	struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;



	dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
@@ -9906,7 +9906,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 
static bool is_dp_capable_without_timing_msa(struct dc *dc,

					     struct amdgpu_dm_connector *amdgpu_dm_connector)

{

	uint8_t dpcd_data;

	u8 dpcd_data;

	bool capable = false;



	if (amdgpu_dm_connector->dc_link &&
@@ -9925,7 +9925,7 @@ static bool is_dp_capable_without_timing_msa(struct dc *dc, 
static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,

		unsigned int offset,

		unsigned int total_length,

		uint8_t *data,

		u8 *data,

		unsigned int length,

		struct amdgpu_hdmi_vsdb_info *vsdb)

{
@@ -9980,7 +9980,7 @@ static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 
}



static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,

		uint8_t *edid_ext, int len,

		u8 *edid_ext, int len,

		struct amdgpu_hdmi_vsdb_info *vsdb_info)

{

	int i;
@@ -10021,7 +10021,7 @@ static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 
}



static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,

		uint8_t *edid_ext, int len,

		u8 *edid_ext, int len,

		struct amdgpu_hdmi_vsdb_info *vsdb_info)

{

	int i;
@@ -10037,7 +10037,7 @@ static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 
}



static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,

		uint8_t *edid_ext, int len,

		u8 *edid_ext, int len,

		struct amdgpu_hdmi_vsdb_info *vsdb_info)

{

	struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
@@ -10051,7 +10051,7 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 
static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,

		struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)

{

	uint8_t *edid_ext = NULL;

	u8 *edid_ext = NULL;

	int i;

	bool valid_vsdb_found = false;
@@ -10227,7 +10227,7 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 
}



void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,

		       uint32_t value, const char *func_name)

		       u32 value, const char *func_name)

{

#ifdef DM_CHECK_ADDR_0

	if (address == 0) {
@@ -10242,7 +10242,7 @@ void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 
uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,

			  const char *func_name)

{

	uint32_t value;

	u32 value;

#ifdef DM_CHECK_ADDR_0

	if (address == 0) {

		DC_ERR("invalid register read; address = 0\n");