Commit ae8ed2b0 authored by Hans Zhang's avatar Hans Zhang Committed by Manivannan Sadhasivam
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PCI: dw-rockchip: Reorganize register and bitfield definitions 



Register definitions were scattered with ambiguous names (e.g.,
PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked
hierarchical grouping.

Group registers and their associated bitfields logically. This improves
maintainability and aligns the code with hardware documentation.

Signed-off-by: default avatarHans Zhang <18255117159@163.com>
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarNiklas Cassel <cassel@kernel.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250427125316.99627-3-18255117159@163.com
parent c2f61b84

drivers/pci/controller/dwc/pcie-dw-rockchip.c

+31 −18
Original line number Diff line number Diff line
@@ -33,23 +33,36 @@ 


#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)



/* General Control Register */

#define PCIE_CLIENT_GENERAL_CON		0x0

#define  PCIE_CLIENT_RC_MODE		HIWORD_UPDATE_BIT(0x40)

#define  PCIE_CLIENT_EP_MODE		HIWORD_UPDATE(0xf0, 0x0)

#define  PCIE_CLIENT_ENABLE_LTSSM	HIWORD_UPDATE_BIT(0xc)

#define  PCIE_CLIENT_DISABLE_LTSSM	HIWORD_UPDATE(0x0c, 0x8)



/* Interrupt Status Register Related to Legacy Interrupt */

#define PCIE_CLIENT_INTR_STATUS_LEGACY	0x8



/* Interrupt Status Register Related to Miscellaneous Operation */

#define PCIE_CLIENT_INTR_STATUS_MISC	0x10

#define PCIE_CLIENT_INTR_MASK_MISC	0x24

#define PCIE_SMLH_LINKUP		BIT(16)

#define PCIE_RDLH_LINKUP		BIT(17)

#define PCIE_LINKUP			(PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)

#define  PCIE_RDLH_LINK_UP_CHGED	BIT(1)

#define  PCIE_LINK_REQ_RST_NOT_INT	BIT(2)

#define PCIE_CLIENT_GENERAL_CONTROL	0x0

#define PCIE_CLIENT_INTR_STATUS_LEGACY	0x8



/* Interrupt Mask Register Related to Legacy Interrupt */

#define PCIE_CLIENT_INTR_MASK_LEGACY	0x1c



/* Interrupt Mask Register Related to Miscellaneous Operation */

#define PCIE_CLIENT_INTR_MASK_MISC	0x24



/* Hot Reset Control Register */

#define PCIE_CLIENT_HOT_RESET_CTRL	0x180

#define PCIE_CLIENT_LTSSM_STATUS	0x300

#define  PCIE_LTSSM_ENABLE_ENHANCE	BIT(4)



/* LTSSM Status Register */

#define PCIE_CLIENT_LTSSM_STATUS	0x300

#define  PCIE_SMLH_LINKUP		BIT(16)

#define  PCIE_RDLH_LINKUP		BIT(17)

#define  PCIE_LINKUP			(PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)

#define  PCIE_LTSSM_STATUS_MASK		GENMASK(5, 0)



struct rockchip_pcie {
@@ -161,13 +174,13 @@ static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip) 
static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)

{

	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,

				 PCIE_CLIENT_GENERAL_CONTROL);

				 PCIE_CLIENT_GENERAL_CON);

}



static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)

{

	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,

				 PCIE_CLIENT_GENERAL_CONTROL);

				 PCIE_CLIENT_GENERAL_CON);

}



static int rockchip_pcie_link_up(struct dw_pcie *pci)
@@ -516,7 +529,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev, 
	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);



	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,

				 PCIE_CLIENT_GENERAL_CONTROL);

				 PCIE_CLIENT_GENERAL_CON);



	pp = &rockchip->pci.pp;

	pp->ops = &rockchip_pcie_host_ops;
@@ -562,7 +575,7 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev, 
	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);



	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,

				 PCIE_CLIENT_GENERAL_CONTROL);

				 PCIE_CLIENT_GENERAL_CON);



	rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;

	rockchip->pci.ep.page_size = SZ_64K;