Commit af040a9a authored by Wei-Lin Chang's avatar Wei-Lin Chang Committed by Marc Zyngier
Browse files

KVM: arm64: nv: Fix MI line level calculation in vgic_v3_nested_update_mi() 



The state of the vcpu's MI line should be asserted when its
ICH_HCR_EL2.En is set and ICH_MISR_EL2 is non-zero. Using bitwise AND
(&=) directly for this calculation will not give us the correct result
when the LSB of the vcpu's ICH_MISR_EL2 isn't set. Correct this by
directly computing the line level with a logical AND operation.

Signed-off-by: default avatarWei-Lin Chang <r09922117@csie.ntu.edu.tw>
Link: https://lore.kernel.org/r/20250625084709.3968844-1-r09922117@csie.ntu.edu.tw


[maz: drop the level check from the original code]
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 04c5355b

arch/arm64/kvm/vgic/vgic-v3-nested.c

+1 −3
Original line number Diff line number Diff line
@@ -401,9 +401,7 @@ void vgic_v3_nested_update_mi(struct kvm_vcpu *vcpu) 
{

	bool level;



	level  = __vcpu_sys_reg(vcpu, ICH_HCR_EL2) & ICH_HCR_EL2_En;

	if (level)

		level &= vgic_v3_get_misr(vcpu);

	level = (__vcpu_sys_reg(vcpu, ICH_HCR_EL2) & ICH_HCR_EL2_En) && vgic_v3_get_misr(vcpu);

	kvm_vgic_inject_irq(vcpu->kvm, vcpu,

			    vcpu->kvm->arch.vgic.mi_intid, level, vcpu);

}