Commit af04e65f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2024-09-02' of https://gitlab.freedesktop.org/drm/msm into drm-next 



Updates for v6.12

DPU:
- Fix implement DP/PHY mapping on SC8180X
- Enable writeback on SM8150, SC8180X, SM6125, SM6350

DP:
- Enable widebus on all relevant chipsets

DSI:
- Fix PHY programming on SM8350 / SM8450

HDMI:
- Add support for HDMI on MSM8998

MDP5:
- NULL string fix

GPU:
- A642L speedbin support
- A615 support
- A306 support
- A621 support
- Expand UBWC uapi
- A7xx GPU devcoredump fixes
- A5xx preemption fixes
- cleanups

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGudK7YMiKDhtvYgp=bY64OZZt0UQSkEkSxLo4rLmeVd9g@mail.gmail.com
parents 88a29f8c 15302579

Documentation/devicetree/bindings/display/msm/hdmi.yaml

+26 −2
Original line number Diff line number Diff line
@@ -19,14 +19,15 @@ properties: 
      - qcom,hdmi-tx-8974

      - qcom,hdmi-tx-8994

      - qcom,hdmi-tx-8996

      - qcom,hdmi-tx-8998



  clocks:

    minItems: 1

    maxItems: 5

    maxItems: 8



  clock-names:

    minItems: 1

    maxItems: 5

    maxItems: 8



  reg:

    minItems: 1
@@ -142,6 +143,7 @@ allOf: 
      properties:

        clocks:

          minItems: 5

          maxItems: 5

        clock-names:

          items:

            - const: mdp_core
@@ -151,6 +153,28 @@ allOf: 
            - const: extp

        hdmi-mux-supplies: false



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,hdmi-tx-8998

    then:

      properties:

        clocks:

          minItems: 8

          maxItems: 8

        clock-names:

          items:

            - const: mdp_core

            - const: iface

            - const: core

            - const: alt_iface

            - const: extp

            - const: bus

            - const: mnoc

            - const: iface_mmss



additionalProperties: false



examples:

Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ properties: 
  compatible:

    enum:

      - qcom,hdmi-phy-8996

      - qcom,hdmi-phy-8998



  reg:

    maxItems: 6

drivers/gpu/drm/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ msm-display-$(CONFIG_DRM_MSM_HDMI) += \ 
	hdmi/hdmi_phy.o \

	hdmi/hdmi_phy_8960.o \

	hdmi/hdmi_phy_8996.o \

	hdmi/hdmi_phy_8998.o \

	hdmi/hdmi_phy_8x60.o \

	hdmi/hdmi_phy_8x74.o \

	hdmi/hdmi_pll_8960.o \

drivers/gpu/drm/msm/adreno/a3xx_catalog.c

+11 −0
Original line number Diff line number Diff line
@@ -41,6 +41,17 @@ static const struct adreno_info a3xx_gpus[] = { 
		.gmem  = SZ_128K,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a3xx_gpu_init,

	}, {

		.chip_ids = ADRENO_CHIP_IDS(0x03000620),

		.family = ADRENO_3XX,

		.revn = 308,

		.fw = {

			[ADRENO_FW_PM4] = "a300_pm4.fw",

			[ADRENO_FW_PFP] = "a300_pfp.fw",

		},

		.gmem = SZ_128K,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init = a3xx_gpu_init,

	}, {

		.chip_ids = ADRENO_CHIP_IDS(

			0x03020000,

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+11 −3
Original line number Diff line number Diff line
@@ -145,6 +145,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);

	} else if (adreno_is_a306a(adreno_gpu)) {

		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000010);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000010);

	} else if (adreno_is_a320(adreno_gpu)) {

		/* Set up 16 deep read/write request queues: */

		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
@@ -237,7 +241,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);



	/* Enable Clock gating: */

	if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))

	if (adreno_is_a305b(adreno_gpu) ||

	    adreno_is_a306(adreno_gpu) ||

	    adreno_is_a306a(adreno_gpu))

		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);

	else if (adreno_is_a320(adreno_gpu))

		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
@@ -334,7 +340,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
		gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);



	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */

	if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||

	if (adreno_is_a305(adreno_gpu) ||

	    adreno_is_a306(adreno_gpu) ||

	    adreno_is_a306a(adreno_gpu) ||

	    adreno_is_a320(adreno_gpu)) {

		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,

				AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |